Method for fabricating self-aligned gate of flash memory cell

A method for fabricating a flash memory cell, the method including the steps of:

• A. forming a pad gate structure comprised of silicon dioxide (SiO2) on an active device area of a semiconductor substrate comprised of silicon;
• B. forming a dummy gate structure comprised of silicon nitride (SiN) on said pad gate structure;
• C. implanting a bit line dopant that is an N-type dopant for forming a drain bit line junction within said active device area of said semiconductor substrate to a first side of said dummy gate structure, and for forming a source bit line junction within said active device area of said semiconductor substrate to a second side of said dummy gate structure;
• D. performing a thermal anneal to activate said bit line dopant within said drain and source bit line junctions;
• E. depositing a metal on said drain and source bit line junctions;
• F. performing a silicidation anneal to form a drain bit line silicide from said metal with said drain bit line junction and to form a source bit line silicide from said metal with said source bit line junction;
• G. conformally depositing an interlevel material comprised of silicon dioxide (SiO2) to surround said dummy gate structure;
• H. polishing down said interlevel material until said dummy gate structure is exposed and contained within said interlevel material;
• I. etching away said dummy gate structure to form a gate opening within said interlevel material;
• J. forming spacers comprised of silicon dioxide (SiO2) at sidewalls of said gate opening within said gate opening;
• K. implanting a pocket dopant that is opposite in conductivity type to said bit line dopant;
• L. implanting a channel dopant to adjust a threshold voltage of said flash memory cell;
• M. etching away any exposed portion of said pad gate structure at a bottom wall of said gate opening;
• N. forming a tunnel dielectric structure comprised of silicon dioxide (SiO2) on the semiconductor substrate at the bottom wall of said gate opening;
• O. forming a floating gate structure comprised of one of silicon nitride (SiN) or polysilicon for charge storage within said flash memory cell, on said tunnel dielectric structure within said gate opening;
• P. forming a floating dielectric structure comprised of silicon dioxide (SiO2) on said floating gate structure within said gate opening;
• Q. conformally depositing polysilicon on said floating dielectric structure within said gate opening and on said interlevel material surrounding said gate opening;
• R. polishing away said polysilicon on said interlevel material such that said polysilicon is contained within said gate opening to form a control gate structure;
• S. forming an encapsulating layer of dielectric material comprised of at least one of silicon dioxide (SiO2) and silicon nitride (SiN) to encapsulate said control gate structure within said gate opening to prevent H2 penetration into said control gate structure, said floating dielectric structure, said floating gate structure, or tunnel dielectric structure;
• and
• T. forming interconnect through said interlevel material to said drain and source bit line silicides.