Method of forming integrated circuitry, method of forming a capacitor and method of forming DRAM integrated circuitry

A method of forming a capacitor comprising:

• forming a first capacitor electrode layer over a substrate;
• forming a capacitor dielectric layer over the first capacitor electrode layer, the capacitor dielectric layer having at least one exposed edge terminus;
• forming a second capacitor electrode layer over the capacitor dielectric layer;
• and
• physical vapor depositing a silicon nitride comprising layer over the capacitor dielectric layer exposed edge terminus.

A method of forming a capacitor comprising:

• forming a first capacitor electrode layer over a substrate;
• forming a capacitor dielectric layer over the first capacitor electrode layer, the capacitor dielectric layer having at least one exposed edge terminus;
• forming a second capacitor electrode layer over the capacitor dielectric layer;
• depositing an electrically insulative layer over the second capacitor electrode layer and the capacitor dielectric layer exposed edge terminus;
• and
• anisotropically etching the electrically insulative layer to form an insulative sidewall spacer over the capacitor dielectric layer exposed edge terminus, the insulative sidewall spacer not contacting any portion of the first capacitor electrode layer.

A method of forming a capacitor comprising:

• forming a first capacitor electrode layer over a substrate;
• forming a capacitor dielectric layer over the first capacitor electrode layer, the capacitor dielectric layer having at least one exposed edge terminus;
• forming a second capacitor electrode layer over the capacitor dielectric layer;
• depositing an electrically insulative layer over the second capacitor electrode layer and the capacitor dielectric layer exposed edge terminus;
• anisotropically etching the electrically insulative layer to form an insulative sidewall spacer over the capacitor dielectric layer exposed edge terminus;
• and
• wherein the depositing comprises physical vapor depositing a silicon nitride comprising layer.

A method of forming a capacitor comprising:

• forming a first capacitor electrode layer over a substrate;
• forming a capacitor dielectric layer over the first capacitor electrode layer, the capacitor dielectric layer having at least one exposed edge terminus;
• forming a second capacitor electrode layer over the capacitor dielectric layer;
• depositing an electrically insulative layer over the second capacitor electrode layer and the capacitor dielectric layer exposed edge terminus;
• anisotropically etching the electrically insulative layer to form an insulative sidewall spacer over the capacitor dielectric layer exposed edge terminus;
• and
• wherein the depositing comprises physical vapor depositing to form the electrically insulative layer to -consist essentially of silicon nitride.

A method of forming DRAM integrated circuitry comprising:

• forming a DRAM wordline over a substrate, the DRAM wordline comprising a gate of a DRAM cell field effect transistor which has a pair of source/drain regions;
• forming a DRAM cell capacitor storage node layer in electrical connection with one of the pair of source/drain regions;
• forming a capacitor dielectric layer over the storage node layer;
• forming a DRAM cell capacitor cell electrode layer over the capacitor dielectric layer;
• removing a selected portion of the cell electrode layer and forming an exposed edge terminus of the capacitor dielectric layer;
• after the removing, physical vapor depositing a silicon nitride comprising layer over the cell electrode layer and the edge terminus;
• and
• after the etching, forming a DRAM bit line in electrical connection with the other of the pair of source/drain regions.

A method of forming DRAM integrated circuitry comprising:

• forming a DRAM wordline over a substrate, the DRAM wordline comprising a gate of a DRAM cell field effect transistor which has a pair of source/drain regions;
• forming a DRAM cell capacitor storage node layer in electrical connection with one of the pair of source/drain regions;
• forming a capacitor dielectric layer over the storage node layer;
• forming a DRAM cell capacitor cell electrode layer over the capacitor dielectric layer;
• physical vapor depositing a silicon nitride comprising layer over the cell electrode layer;
• removing selected portions of the physical vapor deposited silicon nitride comprising layer, the cell electrode layer and the capacitor dielectric layer in a common masking step, the removing forming an exposed edge terminus of the capacitor dielectric layer;
• after the removing, depositing an electrically insulative layer over the physical vapor deposited silicon nitride comprising layer and the capacitor dielectric layer edge terminus;
• anisotropically etching the electrically insulative layer to form an insulative sidewall spacer over the capacitor dielectric layer edge terminus;
• and
• after the etching, forming a DRAM bit line in electrical connection with the other of the pair of source/drain regions.

A method of forming DRAM integrated circuitry comprising:

• forming a DRAM wordline over a substrate, the DRAM wordline comprising a gate of a DRAM cell field effect transistor which has a pair of source/drain regions;
• forming an insulative layer outwardly of the DRAM wordline and a capacitor container opening within the insulative layer;
• lining sidewalls of the container opening with a diffusion barrier material;
• forming a DRAM cell capacitor storage node layer within the container opening in electrical connection with one of the pair of source/drain regions;
• forming a capacitor dielectric layer within the container opening over the storage node layer;
• forming a DRAM cell capacitor cell electrode layer within the container opening over the capacitor dielectric layer, the cell electrode layer leaving remaining unfilled volume within the container opening;
• filling the unfilled remaining volume of the container opening with an electrically insulative material;
• after the filling, patterning and removing selected portions of the cell electrode layer;
• after the removing, physical vapor depositing a silicon nitride comprising layer over the substrate;
• and
• after the physical vapor depositing, forming a DRAM bit line in electrical connection with the other of the pair of source/drain regions.