Circuit for providing isolation of integrated circuit active areas

A method for fabricating an integrated circuit in a semiconductor substrate, comprising:

• forming a first pair of transistors having a shared active area;
• forming a second pair of transistors having a shared active area;
• forming a first isolation gate formed between the first and second pairs of transistors;
• forming a third pair of transistors having a stared active area;
• forming a fourth pair of transistors having a shared active area;
• forming a second isolation gate, formed between the third and fourth pairs of transistors;
• and
• cross coupling the first and third pairs of transistors and the second and fourth pairs of transistors such that only one of a pair of transistors having a shared active area is on at a given time.

A method for fabricating an integrated circuit formed in a semiconductor substrate comprising:

• forming a first cross coupled pair of transistors having a shared active area;
• forming a second cross coupled pair of transistors having a shared active area;
• and
• forming an isolation gate formed between the first and second pairs of transistors;
• such that only one of a pair of transistors having a shared active area is on at a given time.

A method for fabricating an integrated circuit in a semiconductor substrate, comprising:

• forming a first transistor having first and second active areas and a gate defining a first channel and coupled to others of the transistors in the circuit,
• forming a second transistor having third and fourth active areas and a gate defining a second channel and coupled to others of the transistors in the circuit, the third active area being disposed adjacent tie second active area,
• forming a third transistor sharing the fourth active area with the second transistor and having a fifth active area and a gate defining a third channel and coupled to others of the transistors in the circuit;
• forming an isolation gate defining an isolation channel between the second and third active areas;
• coupling the isolation gate to a voltage such that the isolation gate always reverse biases the isolation channel, the isolation channel having the same structure as at least one of the first, second, and third channels, such that only one of a pair of transistors having a shared active area is on at a given time.

A method for fabricating an integrated circuit in a semiconductor substrate, comprising:

• forming a first field-effect transistor having first and second active areas and a gate coupled to others of the transistors in the circuit,
• forming a second field-effect transistor having third and fourth active areas and a gate coupled to others of the transistors in the circuit, the third active area being disposed adjacent the second active area,
• forming a third field-effect transistor sharing the fourth active area with the second transistor and having a fifth active area and a gate coupled to others of the transistors in the circuit;
• forming an isolation gate disposed directly over the substrate and defining an isolation channel between the second and third active areas;
• coupling the isolation gate to a voltage such that the isolation gate always reverse biases the isolation channel, such that only one of a pair of transistors having a shared active area is on at a given time.

A method for fabricating an integrated circuit in a semiconductor substrate, comprising:

• a plurality of field-effect transistors disposed in a semiconductor substrate and interconnected so as to perform a circuit function;
• forming a first field-effect transistor having first and second active areas in the substrate for performing the circuit function;
• forming a second field-effect transistor having third and fourth active areas in the substrate for performing the circuit function, the third active area being disposed adjacent the second active area;
• forming a third field-effect transistor sharing the fourth active area with the second transistor and further having a fifth active area separated from the first and second transistors;
• forming an isolation gate defining an isolation channel disposed directly between the third and fourth active areas;
• forming a connection to a constant voltage sufficient to reverse-bias the isolation channel as the first and second transistors perform the circuit function, such that only one of a pair of transistors having a shared active area is on at a given time.

A method for fabricating an integrated circuit structure, comprising:

• forming a continuous doped layer having first second, third, fourth, and fifth active areas formed directly in the substrate;
• forming first, second, third, and fourth gates disposed between all mutually adjacent ones of the active areas for forming first, second, third, and fourth channels all having the same structure;
• forming a connection for coupling the second gate to a constant potential for reverse biasing the second channel at all times;
• forming further connections for coupling the first, third, and fourth gates to perform a circuit function.