Field effect transistor and method of manufacturing same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHidekazu Oda, Tomohiro Yamashita, Shuichi Ueno
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Abstract
A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.
Claims13
A method of manufacturing a field effect transistor, comprising the steps of:
- (a) preparing a semiconductor substrate having a surface;
- (b) forming an insulating film on said surface of said semiconductor substrate;
- (c) forming a conductive material to cover said insulating film;
- (d) patterning said conductive material and said insulating film to form a MOS gate;
- (e) implanting an impurity into said surface of said semiconductor substrate around said MOS gate to form first and second diffusion regions;
- (f) forming a mask so as to expose a part of a top surface of said conductive material which is far from said second diffusion region and to cover a top surface of said second diffusion region;
- (g) forming a metal film over said surface of said semiconductor substrate using said mask;
- (h) heating said metal film to form a compound of said metal film and the part of the top surface of said conductive material which is far from said second diffusion region;
- (i) forming an interlayer insulating film to cover the surface of said semiconductor substrate;
- and
- (j) forming a capacitor connected to said second diffusion region via said interlayer insulating film.
A method of manufacturing a field effect transistor, comprising the steps of:
- a) preparing a semiconductor substrate having a surface;
- (b) forming an insulating film on said surface of said semiconductor substrate:
- (c) forming a conductive material to cover said insulating film;
- (d) patterning said conductive material and said insulating film to form a MOS gate;
- (e) implanting an impurity into said surface of said semiconductor substrate around said MOS gate to form first and second diffusion regions;
- (f) forming a mask so as to expose said first diffusion region and to cover a top surface of said second diffusion region;
- (g) forming a metal film over said surface of said semiconductor substrate using said mask;
- (h) heating said metal film to form a compound of said metal film and said first diffusion region;
- (i) forming an interlayer insulating film to cover the surface of said semiconductor substrate, and
- (j) forming a capacitor connected to said second diffusion region via said interlayer insulating film.
The method according to claim, 8, further comprising the steps of:
- (k) forming an insulating material over a surface of a resultant structure provided in step (e);
- (l) etching back said insulating material to leave said insulating material around said MOS gate as a sidewall;
- and
- (m) implanting an impurity into said surface of said semiconductor substrate using said MOS gate and said sidewall as a mask to form third and fourth diffusion regions,
- said steps (k) to (m) being performed between said steps (e) and (f).
Dependencies are inferred from the claim text.