Transistor with shaped gate electrode and method therefor
AssigneeMotorola, Inc.
InventorsWilliam J. Taylor, Jr., Srikanth B. Samavedam, Nigel Cave
Life of this patent
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Abstract
A transistor structure includes a retrograde gate structure (112) that is narrower at the end that interfaces with the gate dielectric (120) than it is at the opposite end and method for manufacture of such a structure. The retrograde gate structure (112) is formed by depositing a layer of gate material (104) that has varying composition in the vertical direction. The differentiation in composition causes varying lateral etch rate characteristics along the vertical direction of the gate structure (112) such that increased etching of the gate material (104) occurs near the interface with the gate dielectric layer (102).
Claims16
A method for forming a transistor, comprising the steps of:
- providing a substrate having at least a semiconductor portion, the semiconductor portion having a top surface;
- forming an insulating layer on the top surface;
- forming a polysilicon layer overlying the insulating layer, wherein the polysilicon layer contains an impurity which has an effect on an etch rate of polysilicon, wherein the impurity has a concentration profile which varies with distance from the top surface;
- providing a mask over the polysilicon layer to define a gate under the mask, wherein the gate has an upper region near the mask and a lower region near the top surface;
- selecting an etching material which has an etch rate of polysilicon which is affected by the impurity;
- etching the polysilicon layer around the gate with the etching material so that after etching the polysilicon layer, the upper region of the gate is wider than the lower region of the gate;
- performing a halo implant at a tilt angle using the lower region of the gate to mask the halo implant;
- performing a relatively light dose implant through the top surface to form a light implant region aligned with an edge of the upper region of the gate;
- forming a sidewall spacer adjacent to the gate portion;
- performing a relatively heavy dose implant through the top surface using the sidewall spacer to mask the relatively heavy dose implant;
- and
- heating the substrate so that the light implant region diffuses to have a relatively small overlap with the lower region of the gate.
A method for forming a transistor, comprising the steps of:
- providing a substrate having at least a semiconductor portion, the semiconductor portion having a surface;
- forming an insulating layer on the surface;
- forming a relatively thin polysilicon layer overlying the insulating layer;
- introducing a first impurity of a first concentration in at least a first portion of the relatively thin polysilicon layer, wherein the first impurity has an effect on an etch rate of polysilicon;
- forming a relatively thick polysilicon layer on the relatively thin layer of polysilicon;
- providing a mask over the relatively thick polysilicon layer to define a first gate under the mask, wherein the first gate has an upper region in the relatively thick polysilicon layer and a lower region in the first portion of the relatively thin polysilicon layer;
- selecting an etching material which has an etch rate of polysilicon which is affected by the impurity;
- etching the relatively thick and relatively thin polysilicon layers around the first gate with the etching material so that after etching the relatively thick and relatively thin polysilicon layers, the upper region of the first gate is wider than the lower region of the first gate;
- performing a first relatively light implant through the surface aligned with an edge of the upper region of the first gate;
- forming a first sidewall spacer adjacent to the first gate;
- and
- performing a first relatively heavy implant through the surface using the first sidewall spacer to mask the first relatively heavy implant.
Dependencies are inferred from the claim text.