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US 6,475,810 B1Granted
Method of manufacturing embedded organic stop layer for dual damascene patterning
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsMei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu, Simon Chooi, Yakub Aliyu
Life of this patent
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Abstract
A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.
Claims24
A method for forming a interconnect opening comprising:
- providing a semiconductor structure having a first dielectric layer and a lower interconnect;
- forming an organic stop layer over said first dielectric layer and said lower interconnect;
- forming a stack dielectric layer over said organic stop layer;
- patterning and etching said stack dielectric layer to form an upper interconnect opening using said organic stop layer as a protective cover;
- in a separate step from the above patterning step, removing said organic stop layer to expose said lower interconnect.
2 more elements
A method for forming a dual damascene opening comprising:
- providing a semiconductor structure;
- forming a first dielectric layer having a lower interconnect over said semiconductor structure;
- forming an organic stop layer over said first dielectric layer and said lower interconnect;
- forming a second and third dielectric layers in sequence to form a stack dielectric layer over said organic stop layer;
- patterning the stack dielectric layers to form a dual damascene opening exposing said organic stop layer using the organic stop layer as a protective cover for the interconnect and a prevention of contamination of dielectric layers by said lower interconnect during etching;
- removing said organic stop layer to expose said lower interconnect.
3 more elements
A method for forming a dual damascene opening comprising:
- providing a semiconductor structure;
- forming a first dielectric layer having a lower interconnect over said semiconductor structure;
- forming an organic stop layer over said first dielectric layer and said lower interconnect;
- forming a second and third dielectric layers in sequence to form a stack dielectric layer over said organic stop layer;
- patterning the stack dielectric layers to form a dual damascene opening exposing said organic stop layer using the organic stop layer as a protective cover for the interconnect and a prevention of contamination of dielectric layers by said lower interconnect during etching;
- in a separate step from the above patterning step, removing said organic stop layer to expose said lower interconnect.
3 more elements
Dependencies are inferred from the claim text.