Clock circuit and method of designing the same

A method of designing a clock circuit for supplying a clock signal to each of a plurality of synchronous devices in an integrated circuit, the method comprising:

• a first step of determining, for a non-inverting operation synchronous device which operates on a rising edge of the clock signal, a first operation response time between inputting of the clock signal and the operation of the non-inverting operation synchronous device and determining, for an inverting operation synchronous device which operates on a falling edge of the clock signal, a second operation response time between the inputting of the clock signal and the operation of the inverting operation synchronous device;
• and
• a second step of allocating, as a clock delay value, either of the first and second operation response times to each of the plurality of synchronous devices, while ensuring an operation of the integrated circuit, and replacing that one of the plurality of synchronous devices to which the first operation response time has been allocated as the clock delay value with the non-inverting operation synchronous device, while replacing that one of the plurality of synchronous devices to which the second operation response time has been allocated as the clock delay value with the inverting operation synchronous device.

A clock circuit for supplying a clock signal to each of a plurality of synchronous devices in an integrated circuit, wherein

• the clock signal is supplied to each of the plurality of synchronous devices in accordance with a selected clock delay value which is a clock delay value allocated to each of the synchronous devices, while an operation of the integrated circuit is ensured,
• the selected clock delay value being selected from a group of discrete clock delay values composed of a finite number of discrete values to be allocated as the respective clock delay values to the plurality of synchronous devices.