Fault resilient/fault tolerant computing
AssigneeMarathon Technologies Corporation
InventorsThomas D. Bissett, Paul A. Leveille, Erik Muench
Life of this patent
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Abstract
A fault tolerant/fault resilient computer system includes at least two compute elements connected to at least one controller. Each compute element has clocks that operate asynchronously to clocks of the other compute elements. The compute elements operate in a first mode in which the compute elements each execute a first stream of instructions in emulated clock lockstep, and in a second mode in which the compute elements each execute a second stream of instructions in instruction lockstep. Each compute element may be a multi-processor compute element.
Claims14
A fault tolerant/fault resilient computer system, comprising:
- at least two compute elements;
- and
- at least one controller connected to the at least two compute elements;
- wherein:
- each of the compute elements has clocks that operate asynchronously to clocks of the other compute elements,
- the compute elements each execute a stream of instructions,
- upon issuing an I/O request instruction from the stream of instructions, each compute element enters a halted state, and
- each compute element is removed from the halted state by an interrupt generated upon completion of the I/O request instruction.
Dependencies are inferred from the claim text.