Time synchronizing method for switching system
AssigneeLG Information & Communications, Ltd.
InventorsNam Soo Yeo, Ki Moon Nham
Life of this patent
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Abstract
A time management method for a switching system include: periodically checking a failure state of an HW time using an OMDC; setting the HW time or a user time as an initial system time in accordance with the failure state of the HW time; resetting a system time by periodically comparing the HW time or an MP time, in which an IPC delay is considered, with an OMP time; requesting the initial system time to an OMP; setting an initial MP time as the received OMP time; and periodically comparing the MP time in which the IPC delay is considered with the OMP time and thereby resetting the MP time.
Claims29
In a time management apparatus for a switching system provided with an OMP (operating and maintenance processor) which is a master processor of a system time management, an OMDC (operating maintenance device controller) which provides an HW time which is accessed by an HW time device to the, OMP and an MP (maintenance processor) connected with the, OMP, a time setting method for a switching system, comprising:
- periodically checking a failure state of an HW time;
- setting an initial system time in accordance with the failure state of the HW time;
- registering a periodical cycle signal with an OS (operation system);
- and
- periodically comparing the HW time or an MP time with an OMP time, being operated in a regular cycle in accordance with the. cycle signal, and resetting a system time in accordance with the failure state of the HW time and at least one IPC (inter processor communication) delay.
In a time management apparatus for a switching system which includes an OMP which sets a system time and an MP which is connected with the OMP and periodically requests an OMP time, an MP time setting method for a switching system, comprising:
- requesting an initial system time to the OMP;
- setting an initial MP time as an OMP time which is received;
- registering a periodical cycle signal with an OS;
- and
- periodically computing a time difference between the OMP time and the MP time in accordance with the cycle signal, -computing an IPC .(inter processor communication) delay of the OMP time, and thereby resetting the MP time in accordance with the time difference. and the IPC delay.
In a time management apparatus for a switching system provided with an OMP which is a master processor of a system time management, an OMDC which provides an HW time which is accessed by an HW time device to the OMP and an MP connected with the OMP, a time management method for a switching system, comprising:
- periodically checking a failure state of an HW time;
- setting an initial system time in accordance with the failure state of the HW time;
- periodically computing a time difference between an OMP time and the HW. time or an MP time in accordance with the cycle signal, computing an IPC (inter processor communication) delay of the HW time or the MP time, and thereby resetting the system time in accordance with the failure state of the HW time, the time difference, and the IPC delay;
- requesting the initial system time to the OMP;
- setting an initial MP time as the received OMP time;
- and
- periodically computing a time difference between the OMP time and the MP time in accordance with the cycle signal, computing the IPC delay of the OMP time, and thereby resetting the MP time in accordance with the time difference and the IPC delay.
Dependencies are inferred from the claim text.