Apparatus comprising clock control circuit, method of controlling clock signal and device using internal clock signal synchronized to external clock signal

A clock control circuit, comprising:

• a forward-pulse delay line which is configured by cascading a plurality of stages of forward-pulse delay circuits to delay an inputted signal by propagating said inputted signal with a predetermined delay time, and delays a forward pulse, which corresponds to a second clock signal obtained by delaying a first clock signal by a first delay time, by a second delay time corresponding to the difference between the period of said first clock signal and said first delay time,
• a rearward-pulse delay line which is configured by cascading a plurality of stages of rearward-pulse delay circuits to delay an inputted signal by propagating said inputted signal with a predetermined delay time, and, by being set to the reset state of a stage corresponding to the stage of said forward-pulse delay line where said forward pulse was propagated after said second delay time from the start of propagation of said forward pulse by said forward-pulse delay line, and also by being set to the set state of stages corresponding to the stages of said forward-pulse delay line from the 1st stage to the stage where said forward pulse was propagated, propagates the rearward pulse generated in said stage in the reset state by said stages in the set state and outputs said rearward pulse from the 1st stage,
• a state-holding device which is configured with a number of stages corresponding to the number of stages of said forward-pulse delay line and said rearward-pulse delay line, and has a plurality of state-holding circuits to control propagation of said rearward pulse by said rearward-pulse delay line by turning stages corresponding to the stages of said forward-pulse delay line where said forward pulse was propagated during a one polarity pulse duration of said first clock signal to the set state and also by turning stages corresponding to the stages where said rearward pulse was propagated during a predetermined time from the edge of said first clock signal to the reset state,
• a forward-pulse detecting device to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages of said forward-pulse delay line, and
• an electric power consumption control device to control electric power consumption of said rearward-pulse delay circuits, corresponding to the detected result of said forward-pulse detecting device.

A clock control circuit, comprising:

• a forward-pulse delay line which is configured by cascading a plurality of stages of forward-pulse delay circuits to delay an inputted signal by propagating said inputted signal with a predetermined delay time, and delays a forward pulse, which corresponds to a second clock signal obtained by delaying a first clock signal by a first delay time, by a second delay time corresponding to the difference between the period of said first clock signal and said first delay time,
• a rearward-pulse delay line which is configured by cascading a plurality of stages of rearward-pulse delay circuits to delay an inputted signal by propagating said inputted signal with a predetermined delay time, and, by being set to the reset state of a stage corresponding to the stage of said forward-pulse delay line where said forward pulse was propagated after said second delay time from the start of propagation of said forward pulse by said forward-pulse delay line and also by being set to the set state of stages corresponding to the stages of said forward-pulse delay line from the 1st stage to the stage where said forward pulse was propagated, propagates a rearward pulse which is generated in said stage in the reset state by taking in said first clock signal selectively by said stages in the set state and outputs said rearward pulse from the 1st stage,
• a state-holding device which is composed of a number of stages corresponding to the number of stages of said forward-pulse delay line and said rearward-pulse delay line, and has a plurality of state-holding circuits to control propagation of said rearward pulse by said rearward-pulse delay line by turning stages corresponding to the stage of said forward-pulse delay line where said forward pulse was propagated during a one polarity pulse duration of said first clock signal to the set state, and also by turning stages corresponding to the stages where said rearward pulse was propagated for only a predetermined time from the edge of said first clock signal to the reset state,
• a forward-pulse detecting device to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages, and
• an electric power consumption control device to control electric power consumption by controlling the supply of power supply voltage to said rearward-pulse delay circuits, corresponding to the detected result of said forward-pulse detecting device.

A clock control circuit, comprising:

• a forward-pulse delay line which is configured by cascading a plurality of stages of forward-pulse delay circuits to delay an inputted signal by propagating said inputted signal with a predetermined delay time, and delays a forward pulse, which corresponds to a second clock signal obtained by delaying a first clock signal by a first delay time, by a second delay time corresponding to the difference between the period of said first clock signal and said first delay time,
• a rearward-pulse delay line which is configured by cascading a plurality of stages of rearward-pulse delay circuits to delay an inputted signal by propagating said inputted signal with a predetermined delay time, and, by being set to the reset state of a stage corresponding to the stage of said forward-pulse delay line where said forward pulse was propagated after said second delay time from the start of propagation of said forward pulse by said forward-pulse delay line, and also by being set to the set state of stages corresponding to the stages of said forward-pulse delay line from the 1st stage to the stage where said forward pulse was propagated, propagates a rearward pulse generated in said stage in the reset state by said stages in the set state and outputs it from the 1st stage,
• a state-holding device which is composed of a number of stages corresponding to the number of stages of said forward-pulse delay line and said rearward-pulse delay line, and has a plurality of state-holding circuits to control propagation of said rearward pulse by said rearward-pulse delay line by turning a stage corresponding to the stage of said forward-pulse delay line where said forward pulse was propagated during a one polarity pulse duration of said first clock signal to the set state, and also by turning stages corresponding to the stages where said rearward pulse was propagated for only a predetermined time from the edge of said first clock signal to the reset state,
• a forward-pulse detecting device to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages, and
• an electric power consumption control device to control electric power consumption by controlling the supply of input signals to said rearward-pulse delay circuits, corresponding to the detected result of said forward-pulse detecting device.

A clock control circuit, comprising:

• a forward-pulse delay line, which is configured by cascading a plurality of forward-pulse delay circuits, controlled by a first control signal, to propagate a forward pulse generated in correspondence with a first clock signal,
• a rearward-pulse delay line, which is configured by cascading a plurality of rearward-pulse delay circuits provided in correspondence with said plurality of forward-pulse delay circuits of said forward-pulse delay line, to propagate a rearward pulse in said rearward-pulse delay line by stages corresponding to stages by which said forward pulse has propagated in said forward-pulse delay line to be outputted,
• a state-holding device connected to said forward-pulse delay line and said rearward-pulse delay line, controlled by said first control signal, to turn stages of said rearward-pulse delay line corresponding to stages by which said forward pulse has propagated to the set state, and also turn stages by which said rearward pulse has propagated to the reset state, and
• a forward-pulse detecting device to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages, and
• an electric power consumption control device to control electric power consumption by said rearward-pulse delay circuits corresponding to the result of said forward-pulse detecting device,
• wherein a rearward-pulse delay circuit which is nearest the output side among said rearward-pulse delay circuits connected to said state-holding device which has been turned to the reset state generates said rearward pulse in correspondence with said first clock.

A clock control circuit, comprising:

• a forward-pulse delay line, which is configured by cascading a plurality of forward-pulse delay circuits, controlled by a first control signal, to propagate a forward pulse generated in correspondence with a first clock signal,
• a rearward-pulse delay line, which is configured by cascading a plurality of rearward-pulse delay circuits provided in correspondence with said plurality of forward-pulse delay circuits of said forward-pulse delay line, to propagate a rearward pulse in said rearward-pulse delay line by stages corresponding to stages by which said forward pulse has propagated in said forward-pulse delay line to be outputted,
• a state-holding device connected to said forward-pulse delay line and said rearward-pulse delay line, controlled by said first control signal, to turn stages of said rearward-pulse delay line corresponding to stages by which said forward pulse has propagated to the set state, and also turn stages by which said rearward pulse has propagated to the reset state, and
• a forward-pulse detecting device to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages, and
• an electric power consumption control device to control electric power consumption by said rearward-pulse delay circuits, and also control electric power consumption by at least one of said forward-pulse delay circuits and said state-holding circuits corresponding to the result of said forward-pulse detecting device,
• wherein a rearward-pulse delay circuit which is nearest the output side among said rearward-pulse delay circuits connected to said state-holding device which has been turned to the reset state generates said rearward pulse in correspondence with said first clock.

A clock control circuit, comprising:

• a forward-pulse delay line, which is configured by cascading a plurality of forward-pulse delay circuits, controlled by a first control signal, to propagate a forward pulse generated in correspondence with a first clock signal,
• a rearward-pulse delay line, which is configured by cascading a plurality of rearward-pulse delay circuits provided in correspondence with said plurality of forward-pulse delay circuits of said forward-pulse delay line, to propagate a rearward pulse in said rearward-pulse delay line by stages corresponding to stages by which said forward pulse has propagated in said forward-pulse delay line to be outputted,
• a state-holding device connected to said forward-pulse delay line and said rearward-pulse delay line, controlled by said first control signal, to turn stages of said rearward-pulse delay line corresponding to stages by which said forward pulse has propagated to the set state, and also turn stages by which said rearward pulse has propagated to the reset state,
• a forward-pulse detecting device to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages, and
• an electric power consumption control device to control electric power consumption by controlling the supply of power supply voltage to said rearward-pulse delay circuits corresponding to the result of said forward-pulse detecting device,
• wherein a rearward-pulse delay circuit which is nearest the output side among said rearward-pulse delay circuits connected to said state-holding device which has been turned to the reset state generates said rearward pulse in correspondence with said first clock.

A clock control circuit, comprising:

• a forward-pulse delay line, which is configured by cascading a plurality of forward-pulse delay circuits, controlled by a first control signal, to propagate a forward pulse generated in correspondence with a first clock signal,
• a rearward-pulse delay line, which is configured by cascading a plurality of rearward-pulse delay circuits provided in correspondence with said plurality of forward-pulse delay circuits of said forward-pulse delay line, to propagate a rearward pulse in said rearward-pulse delay line by stages corresponding to stages by which said forward pulse has propagated in said forward-pulse delay line to be outputted,
• a state-holding device connected to said forward-pulse delay line and said rearward-pulse delay line, controlled by said first control signal, to turn stages of said rearward-pulse delay line corresponding to stages by which said forward pulse has propagated to the set state, and also turn stages by which said rearward pulse has propagated to the reset state,
• a forward-pulse detecting device to detect to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages, and
• an electric power consumption control device to control electric power consumption by controlling the supply of power supply voltage to said rearward-pulse delay circuits, and also control electric power consumption by controlling the supply of power supply voltage to at least one of said forward-pulse delay circuits and said state-holding circuits corresponding to the result of said forward-pulse detecting device,
• wherein a rearward-pulse delay circuit which is nearest the output side among said rearward-pulse delay circuits connected to said state-holding device which has been turned to the reset state generates said rearward pulse in correspondence with said first clock.

A clock control circuit, comprising:

• a forward-pulse delay line, which is configured by cascading a plurality of forward-pulse delay circuits, controlled by a first control signal to propagate a forward pulse generated in correspondence with a first clock signal,
• a rearward-pulse delay line, which is configured by cascading a plurality of rearward-pulse delay circuits provided in correspondence with said plurality of forward-pulse delay circuits of said forward-pulse delay line, to propagate a rearward pulse in said rearward-pulse delay line by stages corresponding to stages by which said forward pulse has propagated in said forward-pulse delay line to be outputted,
• a state-holding device connected to said forward-pulse delay line and said rearward-pulse delay line, controlled by said first control signal to turn stages of said rearward-pulse delay line corresponding to stages by which said forward pulse has propagated to the set state, and also turn stages by which said rearward pulse has propagated to the reset state, and
• a forward-pulse detecting device to detect to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages, and
• an electric power consumption control device to control electric power consumption by controlling the supply of power supply input signals to said rearward-pulse delay circuits corresponding to the result of said forward-pulse detecting device,
• wherein a rearward-pulse delay circuit which is nearest the output side among said rearward-pulse delay circuits connected to said state-holding device which has been turned to the reset state generates said rearward pulse in correspondence with said first clock.

A clock control circuit, comprising:

• a forward-pulse delay line, which is configured by cascading a plurality of forward-pulse delay circuits, controlled by a first control signal, to propagate a forward pulse generated in correspondence with a first clock signal,
• a rearward-pulse delay line, which is configured by cascading a plurality of rearward-pulse delay circuits provided in correspondence with said plurality of forward-pulse delay circuits of said forward-pulse delay line, to propagate a rearward pulse in said rearward-pulse delay line by stages corresponding to stages by which said forward pulse has propagated in said forward-pulse delay line to be outputted,
• a state-holding device connected to said forward-pulse delay line and said rearward-pulse delay line, controlled by said first control signal, to turn stages of said rearward-pulse delay line corresponding to stages by which said forward pulse has propagated to the set state, and also turn stages by which said rearward pulse has propagated to the reset state, and
• a forward-pulse detecting device to detect whether said forward pulse was propagated or not in one or a plurality of predetermined stages, and
• an electric power consumption control device to control electric power consumption by controlling the supply of power supply input signals to said rearward-pulse delay circuits, and also control electric power consumption by controlling the supply of the power supply input signals to at least one of said forward-pulse delay circuits and said state-holding circuits corresponding to the result of said forward-pulse detecting device,
• wherein a rearward-pulse delay circuit which is nearest the output side among said rearward-pulse delay circuits connected to said state-holding device which has been turned to the reset state generates said rearward pulse in correspondence with said first clock.

A clock control method, comprising:

• obtaining clock signals synchronized with clock signals inputted to a forward-pulse delay line which is configured by cascading a plurality of stages of forward-pulse delay circuits to delay an inputted signal by propagating said inputted signal with a predetermined delay time, and delays a forward pulse by propagating said forward pulse, by said forward-pulse delay line, a rearward-pulse delay line which is configured by cascading a plurality of stages of rearward-pulse delay circuits to delay an inputted signal by propagating said inputted signal with a predetermined delay time, and delays a rearward pulse by propagating said rearward pulse, and a control device to propagate said rearward pulse by said rearward-pulse delay line in a number of stages corresponding to the number of stages where said forward pulse was propagated by said forward-pulse delay line;
• detecting a number of stages where said forward pulse was propagated by said forward-pulse delay line;
• and
• controlling electric power consumption of said rearward-pulse delay circuits corresponding to the detected result.