System and method for handling instructions occurring after an ISYNC instruction

A processor comprising:

• a fetcher operable for fetching instructions from memory;
• one or more execution units operable for executing the instructions;
• a dispatch unit operable for dispatching the instructions to the one or more execution units;
• a completion unit operable for completing executed instructions;
• circuitry operable for determining if an instruction in the completion unit is a context-synchronizing-required instruction;
• circuitry in the completion unit operable for completing an isync instruction subsequent to completion of the instruction;
• and
• circuitry operable for not flushing instructions fetched subsequent to the isync instruction if the instruction to complete is not a context-synchronizing-required instruction.

A computer program product adaptable for storage on a computer readable medium, the computer program product operable for completing instructions comprising the program steps of:

• determining if an instruction to complete is a context-synchronizing-required instruction;
• completing an isync instruction subsequent to completion of the instruction;
• and
• not flushing instructions fetched subsequent to the isync instruction if the instruction to complete is not a context-synchronizing-required instruction.