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US 6,473,849 B1Granted
Implementing locks in a distributed processing system
AssigneeAdvanced Micro Devices, Inc.
InventorsJames B. Keller, William A. Hughes
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorsJames B. Keller, William A. Hughes
Estimating the term…
A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. The microcode within the lock requesting node transmits a write command to write corresponding node identification data into a lock register in the arbitrating node. The lock requesting node iteratively reads the lock register until it finds its node identification data stored therein with a valid bit set. The lock requesting node then informs all remaining processing nodes to release shared system resources. This is accomplished through a release request bit and a release response bit in each processing node. After completion of lock operations, the lock requesting node sends a message to the arbitrating node to reset the valid bit in the lock register, and a broadcast message to each remaining node to reset the release request bit. In an alternate embodiment, each processing node includes a lock resource register instead of a release response bit. Each remaining processing node writes its node identification data into the lock resource register within the lock requesting processing node when ready to release shared system resources to allow the lock requesting node to establish lock ownership. This informs the lock requesting node to commence lock operations. Lock operations are performed without contention for system resources and without deadlocks among various processing nodes.
In a multiprocessing computer system comprising a plurality of processing nodes interconnected through an interconnect structure, wherein said plurality of processing nodes includes a first processing node, a second processing node and a third processing node, a method of establishing lock ownership for said first processing node comprising:
In a multiprocessing computer system comprising a plurality of processing nodes interconnected through an interconnect structure, wherein said plurality of processing nodes includes a first processing node having ownership of a lock, a second processing node, and a third processing node, a method whereby said first processing node releases said ownership of said lock comprising:
A multiprocessing computer system comprising:
In a system comprising a plurality of nodes, a first node of the plurality of nodes comprising circuitry configured to acquire a lock in the system for the first node, wherein the circuitry is configured to transmit a write command to a lock register located in a second node of the plurality of nodes to begin acquiring a lock, and wherein the circuitry is configured to transmit one or more read commands to read the lock register to verify that the first node is permitted, by the second node, to acquire the lock.
In a system comprising a plurality of nodes, a first node of the plurality of nodes comprising:
Dependencies are inferred from the claim text.