Snoop resynchronization mechanism to preserve read ordering

A computer system comprising:

• a processor comprising:
• a bus interface unit configured to detect a snoop invalidate operation upon a bus to which said processor is coupled;
• and
• a load/store unit coupled to receive a snoop invalidate request from said bus interface unit in response to said snoop invalidate operation, wherein said load/store unit includes:
• a buffer configured to store load memory operations subsequent to said load memory operations probing a data cache;
• and
• control logic coupled to said buffer, said control logic, responsive to a snoop hit corresponding to said snoop invalidate request on a first load memory operation within said buffer, is configured to record an indication of said snoop hit, and wherein said first load memory operation is a hit in said data cache, and wherein, in response to reprobing said data cache with a second load memory operation from said buffer which misses in said data cache and in response to said indication, said control logic is configured to cause said processor to restore its speculative state to a state consistent with a first instruction corresponding to said second load memory operation;
• and
• an input/output (I/O) device for providing communication between said computer system and another computer system to which said I/O device is coupled.

A method for maintaining ordering of load memory operations comprising:

• receiving a snoop invalidate request;
• comparing a snoop address corresponding to said snoop invalidate request to data addresses in a buffer storing a first load memory operation which hits in a data cache and a second load memory operation prior to said first memory operation in program order, said second load memory operation missing said data cache;
• determining that said snoop address hits said first memory operation responsive to said comparing;
• recording an indication responsive to said determining;
• reprobing said second load memory operation in said data cache subsequent to said recording;
• and
• restoring a speculative state of a processor to a state consistent with a first instruction corresponding to said second load memory operation responsive to said reprobing and to said indication.