Method and apparatus for prevent stalling of cache reads during return of multiple data words
AssigneeUnisys Corporation
InventorsSteven T. Hurlock, Stanley P. Naddeo
Life of this patent
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Abstract
In a data processing system comprising a first level cache, a second level cache, and a processor return path, wherein only one of the first level cache and second level cache can control the processor return path at a given time, an improvement comprises a queue disposed between an output of the first level cache and the processor return path to buffer data output from the first level cache so that the first level cache can continue to process memory requests even though the second level cache has control of the processor return path.
Claims6
In a system comprising a first level cache, a second level cache, and a processor return path, wherein only one of the first level cache and second level cache can access the processor return path at a given time, an improvement comprising:
- a queue disposed between an output of the first level cache and the processor return path to buffer data output from the first level cache as a result of a cache hit so that the first level cache can continue to process memory requests even though the second level cache has access to the processor return path.
In a system comprising a first level cache, a second level cache, and a processor return path, wherein only one of the first level cache and second level cache can access the processor return path at a given time, a method comprising:
- temporarily buffering data output from the first level cache to be passed to the processor return path as a result of a cache hit so that the first level cache can continue to process memory requests even though the second level cache has access to the processor return path.
Dependencies are inferred from the claim text.