Load/store unit having pre-cache and post-cache queues for low latency load memory operations

Abstract

A processor has pre-cache and post-cache buffers. The pre-cache (or LS1) buffer stores memory operations which have not yet probed the data cache. The post-cache (or LS2) buffer stores the memory operations which have probed the data cache. As a memory operation probes the data cache, it is moved from the LS1 buffer to the LS2 buffer. Since misses and stores which have probed the data cache do not reside in the LS1 buffer, the scan logic for selecting memory operations from the LS1 buffer to probe the data cache may be simple and low latency, allowing for the load latency to the data cache for load hits to be relatively low. Furthermore, since the memory operations which have probed the data cache have been removed from the LS1 buffer, the simple scan logic may support high performance features such as allowing hits to proceed under misses, etc. Additionally, since the LS2 buffer receives memory operations which have probed the data cache and thus may be waiting for retirement or fill data from memory, reprobing from the LS2 buffer may be less performance critical than probing from the LS1 buffer. Accordingly, the LS2 buffer may be made deeper than the LS1 buffer to queue numerous misses and/or stores. In this fashion, it may be possible to maximize the use of external bus bandwidth to service the misses.

Dependencies are inferred from the claim text.