Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems

A data processing system comprising:

• memory;
• a plurality of processors each operable with the memory for accessing the memory;
• an arbitrator operable with the processors for enabling each of the processors exclusive access to the memory for a predetermined time period on a rotating basis;
• a time loop counter operable with the arbitrator, the time loop counter counting through time values to which the predetermined time periods of exclusive access to the memory for the processors are synchronized on the rotating basis, wherein the time loop counter includes a frame buffered address generator circuit for ensuring that data communicated between the processors and the memory during the predetermined time periods of exclusive access is matched in time;
• and
• a plurality of registers each operable with the time loop counter and each associated with a respective processor, each of the registers having a predetermined offset time value, wherein the arbitrator enables a processor exclusive access to the memory for a predetermined offset time period when the predetermined time value of the register operable with the processor matches the counted time value of the time loop counter.