US 6,473,818 B1 · Apparatus and method in a network interface device for asynchronously generating SRAM full and empty flags using coded read and write pointer values

Abstract

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. Read and write counters are each implemented as gray code counters that increment a corresponding pointer value by changing a single bit. A synchronization circuit selectively sets a full or empty flag based on an asynchronous comparison of the read and write pointer values. Use of gray code counters for the read pointer value and write pointer value ensures accurate comparisons in a multi-clock environment.

Claims20

Dependent claims

A method in a network interface device, the method comprising:

receiving data frames based on a first clock domain at a first interface of the network interface device;
writing the data frames into a random access memory in the network interface based on the first clock domain;
changing a single bit of a write pointer value in response to each occurrence of the writing step;
reading stored data from the random access memory based on a second clock domain independent from the first clock domain;
changing a single bit of a read pointer value in response to each occurrence of the reading step;
forwarding the read data based on the second clock domain to a second interface on the network interface device;
comparing the read pointer value and the write pointer value;
and
selectively setting one of a full and empty flag based on the comparing step;
writing the data to the random access memory based on the binary write address value.

7 more elements

A network interface device, comprising:

a first interface configured to bi-directionally transmit data, wherein the first interface operates according to a first clock domain;
a second interface configured to bi-directionally transmit data, wherein the second interface operates according to a second clock domain;
a random access memory;
a write controller configured for writing data received from the first interface to the random access memory according to the first clock domain, the write controller including a write counter configured for changing a single bit of a write pointer value in response to writing the data into a corresponding memory location in the random access memory;
a read controller configured for reading stored data from the random access memory and outputting the read data to the second interface according to the second clock domain independent from the first clock domain, the read controller including a read counter configured for changing a single bit of a read pointer value in response to reading the stored data from a corresponding memory location in the random access memory;
and
a comparison circuit for selectively determining one of a full condition and an empty condition in the random access memory based on the write pointer value and the read pointer value, independent of the first and second clock domains.

4 more elements

A network interface for passing data frames comprising:

a host bus interface, wherein the host bus interface operates according to a host clock domain;
a network media interface, wherein the network media interface operates according to a network clock domain;
a first random access memory partition;
a second random access memory partition;
a first write controller configured for writing data received from the host bus interface to the first random access memory partition according to the host clock domain, the first write controller including a first write counter configured for changing a single bit of a first write pointer value in response t o writ in g the data in to a corresponding memory location in the first random access memory partition;
a first read controller configured for reading stored data from the first random access memory partition and outputting the read data to the network media interface according to the network clock domain independent from the host clock domain, the first read controller including a first read counter configured for changing a single bit of a first read pointer value in response to reading the stored data from a corresponding memory location in the first random access memory partition;
a comparison circuit configured for selectively determining one of a full condition and an empty condition in the first random access memory partition based on the first write pointer value and the first read pointer value, independent of the host and network clock domains;
a second write controller configured for writing data received from the net work media interface to the second random access memory partition according to the network clock domain, the second write controller including a second write counter configured for changing a single bit of a second write pointer value in response to writing the data into a corresponding memory location in the second random access memory partition;
a second read controller configured for reading stored data from the second random access memory partition and outputting the read data to the host bus interface according to the host clock domain independent from the network clock domain, the second read controller including a second read counter configured for changing a single bit of a second read pointer value in response to reading the stored data from a corresponding memory location in the second random access memory partition;
and
the comparison circuit further configured for selectively determining one of a full condition and an empty condition in the second random access memory partition based on the second write pointer value and the second read pointer value, independent of the host and network clock domains.

8 more elements

Dependencies are inferred from the claim text.

Apparatus and method in a network interface device for asynchronously generating SRAM full and empty flags using coded read and write pointer values

Life of this patent

Apparatus and method in a network interface device for asynchronously generating SRAM full and empty flags using coded read and write pointer values

Life of this patent

Abstract

Claims20