System for optimally tuning a burst length by setting a maximum burst length based on a latency timer value and adjusting the maximum burst length based on a cache line size
AssigneeInternational Business Machines Corporation
InventorsMichael Edward Lyons, Sean Michael McNeal, Michael Anthony Perez
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Abstract
A method and system for choosing an optimal PCI adapter burst length is disclosed. The optimal burst length is automatically determined by the adapter configuration feature of AIX software using a cache-line size of a PCI bridge and the latency timer value of the target PCI adapter as inputs. The method also provides for a user to be able to override the software-calculated setting.
Claims20
A method for performance tuning of PCI adapter burst length, comprising the steps of:
- determining a cache line size of a PCI bridge;
- and
- responsive to determining said cache line size, automatically setting a burst length using said cache line size and a latency timer value of a target PCI adapter for optimally tuning said burst length for said target PdI adapter, including:
- setting a maximum burst length based on said latency timer value;
- and
- adjusting said maximum burst length based on said cache line size.
A computer system for performance tuning of PCI adapter burst length, comprising:
- means for determining a cache line size of a PCI bridge, and
- means for automatically setting a burst length using said cache line size and a latency timer value of a target PCI adapter for optimally tuning said burst length for said target PCI adapter, including:
- means for setting a maximum burst length based on said latency timer value;
- and
- means for adjusting said maximum burst length based on said cache line size.
A computer program product residing on a computer usable medium for providing environmental control and sensing to an information handling system, comprising:
- first instruction means for determining a cache line size of a PCI bridge;
- and
- second instruction means for automatically setting a burst length using said cache line size and a latency timer value of a target PCI adapter for optimally tuning said burst length for said target PCI adapter, including:
- third instruction means for setting a maximum burst length based on said latency timer value;
- and
- fourth instruction means for adjusting said maximum burst length based on said cache line size.
Dependencies are inferred from the claim text.