Circuits, systems, and methods for efficient wake up of peripheral component interconnect controller

A controller for coupling between a computer bus and one or more units compatible with the bus, the controller comprising:

• a first input for receiving a first reset signal issued from the computer bus;
• a second input for receiving a second reset signal;
• circuitry for storing a first set of information which will be cleared in response to assertion of the first reset signal;
• circuitry for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal;
• and
• a plurality of general purpose pins for receiving a configuration signal representative of one or more functions to be performed by the controller, wherein the second set of information comprises the configuration signal.

A controller for coupling between a computer bus and one or more units compatible with the bus, the controller comprising:

• a first input for receiving a first reset signal issued from the computer bus;
• a second input for receiving a second reset signal;
• circuitry for storing a first set of information which will be cleared in response to assertion of the first reset signal;
• circuitry for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal;
• and
• circuitry for responding to interrupts, wherein the second set of information comprises interrupt information.