Scheduling of direct memory access
AssigneeIntel Corporation
InventorJoseph S. Barcelo
Life of this patent
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Abstract
An improved microprocessor system includes an execution arbitrator which arbitrates between core CPU tasks and DMA tasks and allows for multiple priorities among each, and for priorities with respect to each other.
Claims26
A method of operating a computer system having DMA tasks and core tasks, in which at least one of said DMA tasks is generated by one of said core tasks, said method comprising:
- assigning a priority to each of said DMA tasks and core tasks wherein said at least one DMA tasks is assigned a priority that corresponds to a priority of said one core task that generated it;
- and
- executing a task of a highest priority irrespective of whether it is a DMA task or a core task.
Apparatus for managing a computer system having DMA tasks and core tasks to be executed, in which at least one of said DMA tasks is generated by one of said core tasks, said apparatus comprising:
- means for placing all of said DMA tasks in a DMA task queue and all of said core tasks in a core task queue;
- means for assigning a priority to each of said DMA tasks and core tasks wherein said at least one DMA tasks is assigned a priority that corresponds to a priority of said one core task that generated it;
- and
- means for arbitrating between said DMA task queue and said core task queue to determine whether a DMA task or a core task gets executed during any given cycle because of having a highest priority among all of said tasks in both said queues.
A computer system having DMA tasks and core tasks to be executed, comprising:
- means for placing said DMA tasks in a DMA task queue and said core tasks in a core task queue;
- a CPU having means for generating at least one of said DMA tasks by one of said core tasks;
- means for assigning a priority for each of said DMA and core tasks wherein said at least one DMA task is assigned a priority that corresponds to a priority of said one core task that generated it;
- and
- means for executing said tasks in an order that a task of a highest priority gets executed during any given cycle irrespective of whether such task is a DMA task or a core task.
Dependencies are inferred from the claim text.