Encoding and decoding apparatuses and image processing apparatus using the same
AssigneeCanon Kabushiki Kaisha
InventorTadayoshi Nakayama
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AssigneeCanon Kabushiki Kaisha
InventorTadayoshi Nakayama
Estimating the term…
This invention is to provide encoding and decoding apparatuses capable of increasing the processing speed even when a learning RAM need be frequently cleared for encoding or decoding in units of bands, and an image processing apparatus using the same. The encoding or decoding apparatus includes a plurality of learning RAMs (502, 602) for storing learned contents, and switches (521, 523, 525, 621, 623, 725, 630) for setting one of the plurality of learning RAMs in a learning state and the other in the initialized state and switching the state for every band processing. The apparatus also includes a learning RAM (502) for storing learned contents, a band sequence storage memory (702) for dividing encoding into a plurality of sequences in units of bands and storing data corresponding to a current sequence, and a matching detection circuit (704) and AND gate (706) for, when the sequence stored in the band sequence storage memory is different from the sequence of encoding which is progressing, inhibiting the learned contents read out from the learning RAM from being used for encoding.
An encoding/decoding apparatus for encoding/decoding N units of image each having a predetermined size independently and sequentially, comprising:
A method of encoding/decoding N units of image each having a predetermined size independently and sequentially, comprising the steps of:
An encoding/decoding apparatus for encoding/decoding a plurality of units of image independently and sequentially, comprising:
A method of encoding/decoding a plurality of units of image independently and sequentially, comprising the steps of:
Dependencies are inferred from the claim text.
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Image coding: predictors, e.g. intraframe, interframe coding
Image data processing or generation, in general
Term ended 22 Dec 2018 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The present invention relates to encoding and decoding apparatuses, and an image processing apparatus using the same.
Conventionally, image data or page description language (to be abbreviated as PDL hereinafter) data transferred from a computer to an image output device such as a printer is developed for drawing in the output device. Every time the data is developed for drawing, bitmap data is sent to the printer engine section. However, when contents to be developed for drawing are complex, the drawing development speed maybe lower than the drawing speed of the engine section. In this case, bitmap data developed for drawing is temporarily stored in a memory (this memory is called a page memory). After drawing development is complete in units of pages, and the bitmap data is stored in the memory, the bitmap data is sequentially sent to the printer engine section from the top of the page.
Assume that the size of paper on which the data is printed is A3, and the resolution is 600 dpi. In this case, even when the data is binary data in which the number of bits per pixel is 1, the total bitmap data amount becomes as large as 8 MB, and the large-capacity memory increases the printer cost.
FIG. 1 is a block diagram showing the arrangement of an image processing apparatus in which a page memory capacity is reduced by introducing encoding and decoding processing;
FIG. 2 is a block diagram showing an arrangement in which a FIFO for smoothing bitmap data output from a decoding section over time is inserted between the decoding section and the engine section shown in FIG. 1;
FIG. 3 is a block diagram showing the arrangement of an image processing apparatus having a path for outputting bitmap data from the decoding section to the band buffer section in FIG. 1;
FIG. 6 shows an encoding/decoding apparatus according to the first embodiment of the present invention. In this embodiment, two learning RAMs having the same capacity are used.
Referring to FIG. 6, reference numerals 501 to 525 denote the same parts as in the prior art shown in FIG. 5, and a detailed description thereof will be omitted.
Reference numerals 602, 621, 623, and 625 denote parts having the same functions as those of the elements 502, 521, 523, and 525, respectively; 605, a terminal for inputting a band switching signal which is alternately switched to “High” and “Low” every time the band is switched; and 630, a selector for selecting one of the outputs from the two learning RAMs 502 and 602.