Digital phase-locked loop with phase optimal frequency estimation

A circuit, comprising:

• a register circuit arranged to store a control word;
• a variable frequency oscillator coupled to receive the control word, the variable frequency oscillator producing a clock signal having a current frequency corresponding to the control word;
• a phase detector circuit coupled to receive a reference signal and the clock signal, the lock signal having one of a phase lead and a phase lag with respect to the reference signal, the phase detector circuit producing a phase signal having a first state in response to the phase lead and having a second state in response to the phase lag, wherein the phase detector circuit further comprises a shift register circuit, the shift register circuit having plural stages each stage arranged to store a respective phase signal;
• and
• an estimate circuit coupled to the register circuit and the phase detector circuit, the estimate circuit producing a next control word to be stored in the register circuit.

A circuit, comprising:

• a register circuit arranged to store a control word;
• a variable frequency oscillator coupled to receive the control word, the variable frequency oscillator producing a clock signal having a current frequency corresponding to the control word;
• a phase detector circuit coupled to receive a reference signal and the clock signal, the clock signal having one of a phase lead and a phase lag with respect to the reference signal, the phase detector circuit producing a phase signal having a first state in response to the phase lead and having a second state in response to the phase lag;
• and
• an estimate circuit coupled to the register circuit and the phase detector circuit, the estimate circuit producing a next control word to be stored in the register circuit, wherein a next frequency corresponds to the next control word, and wherein the next frequency is substantially half way between the current frequency and a frequency corresponding to a transition between the first and second states.

A circuit, comprising:

• a storage device arranged to store a control signal;
• a variable frequency oscillator coupled to receive the control signal, the variable frequency oscillator producing a clock signal having a current frequency commanding to the control signal;
• a phase detector circuit coupled to receive a reference signal and the clock signal, the clock signal having one of a phase lead and a phase lag with respect to the reference signal, the phase detector circuit producing a phase signal having a first state in response to the phase lead and having a second state in response to the phase lag;
• and
• an estimate device coupled to the storage device and the phase detector circuit the estimate device producing a next control signal to be stored in the storage device, the next control signal corresponding to a next frequency intermediate the current frequency and a frequency corresponding to a transition between the first and second states.

A circuit, comprising:

• a storage device arranged to store a control signal;
• a variable frequency oscillator coupled to receive the control signal, the variable frequency oscillator producing a clock signal having a frequency corresponding to the control signal;
• a phase detector circuit coupled to receive a reference signal and the clock signal, the clock signal having one of a phase lead and a phase lag with respect to the reference signal, the phase detector circuit producing a phase signal having a first state in response to the phase lead and having a second state in response to the phase lag;
• and
• an estimate device coupled to the storage device and the phase detector circuit, the estimate device producing a next control signal to be stored in the storage device, wherein each of the storage device and the storage device comprises a capacitor.

A circuit, comprising:

• a storage device arranged to store a control signal;
• a variable frequency oscillator coupled to receive the control signal, the variable frequency oscillator producing a clock signal having a current frequency corresponding to the control signal;
• a phase or circuit coupled to receive a reference signal and the clock signal, the clock signal having one of a phase lead and a phase lag with respect to the reference signal, the phase detector circuit producing a phase signal having a first state in response to the phase lead and having a second state in response to the phase lag, wherein the phase detector circuit further comprises a shift register circuit, the shift register circuit having plural stages, each stage arranged to store a respective phase signal;
• and
• an estimate device coupled to the storage device and the phase detector circuit, the estimate device producing a next control signal to be stored in the storage device.

A circuit, comprising:

• a storage device arranged to store a control signal;
• a variable frequency oscillator coupled to receive the control signal, the variable frequency oscillator producing a clock signal having a current frequency corresponding to the control signal;
• a phase detector circuit coupled to receive a reference signal and the clock signal, the clock signal having one of a phase lead and a phase lag with respect to the reference signal, the phase detector circuit producing a phase signal having a first state in response to the phase lead and having a second state in response to the phase lag;
• and
• an estimate device coupled to the storage device and the phase detector circuit, the estimate device producing a next control signal to be stored in the storage device, wherein a next frequency corresponds to the next control signal, and wherein a next frequency is substantially half way between the current frequency and a frequency corresponding to a transition between the first and second states.

A method of estimating a frequency, comprising the steps of:

• storing a control signal;
• producing an oscillator signal having a frequency corresponding to a value of the control signal;
• comparing a reference signal to the oscillator signal;
• producing a phase signal in response to a phase transition between the reference signal and the oscillator signal;
• producing a next control signal in response to the phase signal, the next control signal corresponding to a frequency intermediate the frequency corresponding to the value of the control signal and a frequency corresponding to the phase transition.

A method of estimating a frequency, comprising:

• storing a first estimate signal;
• storing a first control signal;
• producing a first oscillator signal having a frequency corresponding to a value of the first control signal;
• comparing a reference signal to the first oscillator signal;
• producing a phase signal in response to the step of comparing;
• storing a second control signal in response to the phase signal;
• and
• correcting the second control signal with the first estimate signal in response to a phase transition of the phase signal.