Method and apparatus for providing deterministic resets for clock divider systems

Abstract

A clock divider system with reset synchronization includes a divider circuit, a synchronizer circuit, and a synchronous delay circuit. The divider circuit has a clock input, a divider reset input, and a divided clock output. The synchronizer has a clock input, and a synchronous reset input, and a synchronized reset output having an active edge aligned with an active edge of the clock. The synchronous delay circuit has a clock input and a synchronized reset input coupled to the synchronized reset output of the synchronizer, and an output coupled to the divider reset input of the divider. A method for providing reset synchronization for a clock divider system includes developing a reset synchronization signal aligned with an active edge of a clock after receiving an asynchronous reset signal, delaying the reset synchronization signal for at least one cycle to provide a delayed reset synchronization signal, and developing a clock divider reset signal from the delayed reset synchronization signal, that is aligned with an active edge of the clock.

Dependencies are inferred from the claim text.