Wide band alias resolving digitally channelized receiver and a memory for use therewith

A digital channelized processor comprising:

• signal translating means for receiving an input signal and outputting a translated signal at a first clock rate;
• digital signal processing means for receiving the translated signal, performing a real time channelization filtering operation at a second clock rate slower than the first clock rate and outputting a plurality of effective filter signals;
• wherein the digital signal processing means further comprises demultiplexing means for separating the translated signal into a plurality of channelized signals and including,
• filtering means for receiving the channelized signals and outputting a plurality of actual filter signals,
• means for selectively shifting the phase of the actual filter signals by a predetermined amount or providing no phase shift of the actual filter signals, and
• means for summing the actual filter signals and outputting one or more the effective filter signals.

A method for modulating an input signal with a digital channelized processor comprising the steps of:

• (a) receiving an input signal and outputting a translated signal at a first clock rate;
• (b) receiving the translated signal, performing a real time channelization filtering operation at a second clock rate slower than the first clock rate, and outputting a plurality of effective filter signals;
• and
• wherein step (b) includes the steps of, (i) separating the translated signal into a plurality of channelized signals, (ii) digitally filtering the channelized signals, (iii) generating a plurality of actual filter signals, (iv) selectively shifting or non-shifting the phase of the actual filter signals, and (v) following step (iv) summing the actual filter signals and outputting at least one effective filter signal.

A digital channelized processor comprising:

• a signal translating circuit that receives an input signal and outputs a translated signal at a first clock rate;
• a digital signal processing device that receives the translated signal, performs a real time channelization filtering operation at a second clock rate slower than the first clock rate and outputs a plurality of effective filter signals;
• a memory circuit that stores the effective filter signals;
• and
• a phase shifter that shifts the phase of the stored effective filter signals,
• an adder that sums the shifted stored effective filter signals at the second clock rate.

A digital channelized processor comprising:

• a first signal translating circuit that receives an input signal and outputs a translated signal at a first clock rate;
• a digital signal processing circuit that receives the translated signal, performs a real time channelization filtering operation at a second clock rate slower than the first clock rate and outputs a plurality of effective filter signals;
• a demultiplexer that separates the translated signal into a plurality of channelized signals and including,
• a plurality of digital filters that receive the channelized signals and output a plurality of actual filter signals,
• respective circuits that selectively shift the phase of the actual filter signals by a predetermined amount or provides zero phase shift of the actual filter signals,
• a signal summer that then adds said actual filter signals and outputs one or more effective filter signals;
• a memory that stores said one or more effective filter signals at said second clock rate;
• a circuit that shifts the phase of the stored effective filter signals,
• an adder that sums the shifted stored effective filter signals at the second clock rate, and
• a second signal translating circuit that combines the summed shifted stored effective filter signals and outputs a modulated output signal at the first clock rate.

A digital channelized processor comprising:

• signal translating means for receiving an input signal and outputting a translated signal at a first clock rate;
• digital signal processing means for receiving the translated signal, performing a real time channelization filtering operation at a second clock rate slower than the first clock rate and outputting a plurality of effective filter signals;
• wherein the digital signal processing means further comprises demultiplexing means for separating the translated signal into a plurality of channelized signals and including,
• filtering means for receiving the channelized signals and outputting a plurality of actual filter signals;
• means for selectively shifting the phase of the actual filter signals by a predetermined amount or providing no phase shift of the actual filter signals,
• adding means for then summing the actual filter signals and outputting one or more the effective filter signals;
• memory means for storing said one or more effective filter signals at the second clock rate or at a third clock rate slower than the second clock rate;
• another means for shifting the phase of the stored effective filter signals by a predetermined amount, and
• another adding means for summing the shifted stored effective filter signals at the second clock rate.

A method for modulating an input signal with a digital channelized processor comprising the steps of:

• (a) receiving an input signal and outputting a translated signal at a first clock rate;
• (b) receiving the translated signal, performing a real time channelization filtering operation at a second clock rate slower than the first clock rate, and outputting a plurality of effective filter signals;
• wherein step (b) includes the steps of, (i) separating the translated signal into a plurality of channelized signals, (ii) digitally filtering the channelized signals, (iii) generating a plurality of actual filter signals, (iv) selectively shifting or non-shifting the phase of the actual filter signals, and (v) following step (iv) summing the actual filter signals and outputting one or more effective filter signals;
• (c) storing the effective filter signals in a memory at said second clock rate or at a third clock rate slower than the second clock rate;
• (d) shifting the phase of the stored effective filter signals and summing the shifted stored effective filter signals at the second clock rate;
• and
• (e) translating the summed shifted stored effective filter signals and outputting a modulated output signal at the first clock rate.