Synchronous semiconductor memory device capable of high speed reading and writing
AssigneeMitsubishi Denki Kabushki Kaisha
InventorTsukasa Ooishi
Life of this patent
Estimating the term…
Abstract
An address input is received earlier than data input, and a result of decoding of a column address at the time of writing and results of substitution determination for a redundancy memory column are held in a latch circuit corresponding to each bank. When the data arrives at the bank, the data is immediately written to each bank, utilizing the results of address processing. Operation frequency of the chip is not limited by the conventionally experienced wasteful wait time for the data in the process of writing, and efficient data input/output is possible.
Claims7
A synchronous semiconductor memory device receiving an address signal in synchronization with a clock signal and inputting/outputting data, comprising:
- a memory array having a plurality of memory cells arranged in a matrix of rows and columns, said memory array being divided into a plurality of memory areas;
- and
- a plurality of delay shift circuits provided corresponding to said plurality of memory areas respectively, each outputting, in a reading operation, a selecting signal selecting a part of corresponding said memory area in response to said address signal, and in a writing operation, each outputting said selecting signal with a delay by a unit of a period of said clock signal as compared with said reading operation, in response to said address signal.
A synchronous semiconductor memory device receiving an address signal and a control signal in synchronization with a clock signal and inputting/outputting data, comprising:
- a memory array having a plurality of memory cells arranged in a matrix of rows and columns, said memory array being divided into a plurality of memory areas;
- and
- a plurality of flag holding circuits, each flag holding circuit provided corresponding to a respective memory area in the plurality of memory areas, each holding a read flag indicating a read operation designated by said control signal and a write flag indicating a write operation designated by said control signal.
Dependencies are inferred from the claim text.