Semiconductor memory device

A synchronous dynamic memory comprising:

• a plurality of bit lines;
• a plurality of word lines;
• a plurality of memory cells;
• a row address decoder;
• a column address decoder including a pre-decoder and a shift register which receives an output signal of said pre-decoder;
• a selector which selects one or more of said plurality of bit lines on the basis of output signals of said shift register;
• and
• a mode register;
• wherein said shift register forms a first continuous select signal corresponding to a sequential action and a second continuous select signal corresponding to an interleave action, and
• wherein one of said sequential action and said interleave action is designated by said mode register.

A double data rate synchronous dynamic memory comprising:

• a plurality of bit lines;
• a plurality of word lines;
• a plurality of memory cells;
• a row address decoder;
• a column address decoder including a pre-decoder and a circuit which receives an output signal of said pre-decoder;
• a selector which selects one or more of said plurality of bit lines on the basis of output signals of said shift register;
• a mode register;
• and
• an address register which stores an address signal used for a write operation;
• wherein said circuit forms a first continuous select signal corresponding to a sequential action and a second continuous select signal corresponding to an interleave action,
• wherein one of said sequential action and said interleave action is designated by said mode register, and
• wherein said address signal, delayed by said address register, is supplied to said pre-decoder.