Bitline/dataline short scheme to improve fall-through timing in a multi-port memory
AssigneeCypress Semiconductor Corporation
InventorsJunfei Fan, Jeffery Scott Hunt, Daniel E. Cress
Life of this patent
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Abstract
An apparatus comprising a memory array having a first port and a one or more other ports and a control circuit configured to couple (i) a bitline of the first port to a corresponding bitline of the one or more other ports and (ii) a dataline of the first port to a corresponding dataline of the one or more other ports in response to the first port and the one or more other ports accessing a common address.
Claims20
An apparatus comprising:
- a memory array having a first port and one or more other ports;
- and
- a control circuit configured to couple (i) a bitline of said first port to a corresponding bitline of said one or more other ports and (ii) a dataline of said first port to a corresponding dataline of said one or more other ports in response to a common address accessing said first port and said one or more other ports.
An apparatus for bypassing a memory cell in a multi-port memory having a first port and one or more other ports comprising:
- means for detecting a common address accessing multiple ports;
- means for coupling a first port bitline to one or more other port bitlines;
- and
- means for coupling a first port dataline to one or more other port datalines.
A method of bypassing a multi-port memory cell comprising the steps of:
- (A) detecting a common address accessing multiple ports;
- (B) coupling a first port bitline to one or more other port bitlines;
- and
- (C) coupling a first port dataline to one or more other port datalines.
Dependencies are inferred from the claim text.