Low power read circuitry for a memory circuit based on charge redistribution between bitlines and sense amplifier

A memory circuit having low power read capability, comprising:

• means for enabling a wordline pursuant to commencing a memory read cycle with respect to a particular cell in said memory circuit based on a plurality of address signals;
• means for waiting for a first selected period of time until a voltage level on a bitline associated with said particular cell substantially reaches a predetermined sense level responsive to said wordline being driven high;
• means for disabling said wordline so as to stop driving said bitline;
• means for waiting for a second selected period of time until a sense amplifier operable with said bitline substantially reaches said predetermined sense level by a charge redistribution between said sense amplifier and said bitline;
• means for enabling said sense amplifier for sensing a data value based on said predetermined sense level developed thereon;
• and
• precharge circuitry to precharge said bitline substantially at the same time when said sense amplifier is enabled.

A memory circuit, comprising:

• means to initiate a memory read operation with respect to a particular memory cell based on a plurality of address signals and a START signal, said plurality of address signals and said START signal operating to drive a selected wordline associated with said particular memory cell high;
• a reference wordline driver operating responsive at least in part to said START signal to drive a reference wordline associated with at least one reference cell structure, wherein a pair of complementary reference bitlines coupled to said at least one reference cell are operable to generate a voltage signal after a finite time has elapsed from said START signal;
• and
• means to generate a STOP signal when said voltage signal developed on said one of said pair of complementary reference bitlines reaches a particular level,
• wherein said STOP signal operates to deactivate said selected wordline and activates thereafter a sense amplifier operably coupled to said particular memory cell via a pair of complementary bitlines, said sense amplifier operating to sense a data value stored in said particular memory cell based on a charge redistribution between said sense amplifier's internal nodes and said pair of complementary bitlines after said selected wordline is deactivated.

A low power read operation method for a memory circuit, comprising the steps:

• commencing a memory read cycle with respect to a particular cell in said memory circuit based on a plurality of address signals, said plurality of address signals operating to drive a selected wordline associated with said particular cell high;
• generating a control signal based on a reference cell read operation;
• driving said selected wordline low responsive to said control signal;
• and
• activating a sense amplifier operably coupled to said particular memory cell via a pair of complementary bitlines, said sense amplifier operating to latch a data value stored in said particular cell based on a charge redistribution between said sense amplifier's internal nodes and said pair of complementary bitlines after said selected wordline is deactivated.

A memory instance, comprising:

• means for commencing a memory read cycle with respect to a particular cell in said memory instance based on a plurality of address signals and a START signal, said plurality of address signals and said START signal operating to drive a selected wordline associated with said particular cell high;
• means for generating a STOP signal based on a reference cell read operation;
• means for driving said selected wordline low responsive to said STOP signal;
• and
• means for activating a sense amplifier operably coupled to said particular memory cell via a pair of complementary bitlines, said sense amplifier operating to latch a data value stored in said particular cell based on a charge redistribution between said sense amplifier's internal nodes and said pair of complementary bitlines after said selected wordline is deactivated.