Semiconductor memory device having memory cell array structure with improved bit line precharge time and method thereof

A semiconductor memory device comprising:

• memory cell blocks arranged in a memory cell array structure, each of the memory cell blocks having a plurality of memory cells therein;
• a first sense amplifier unit, arranged between two adjacent memory cell blocks and shared by the two adjacent memory cell blocks, that senses and amplifies data of the memory cells;
• a second sense amplifier unit connected to a memory cell block at an edge of the memory cell array structure, that senses and amplifies data of the memory cells;
• and
• a dummy capacitor region having a plurality of capacitors connected between a power supply and either a dummy bit line or a complementary dummy bit line, the dummy bit line and the complementary bit line being respectively connected to a bit line and a complementary bit line of the memory cell block at the edge of the memory cell array structure.

A semiconductor memory device comprising:

• memory cell blocks arranged in a memory cell array structure, each of the memory cell blocks having a plurality of memory cells therein;
• a first sense amplifier unit, arranged between two adjacent memory cell blocks and shared by the two adjacent memory cell blocks, that senses and amplifies data of the memory cells;
• a second sense amplifier unit connected to a memory cell block at an edge of the memory cell array structure, that senses and amplifies data of the memory cells;
• and
• a dummy capacitor region having a plurality of capacitors connected between a dummy bit line and a complementary dummy bit line, both ends of the capacitors being connected respectively to a bit line and a complementary bit line of the memory cell block at the edge of the memory cell array structure and being connected to a power supply.

A method of precharging a bit line in a semiconductor memory device having a common sense amplifier structure, comprising:

• precharging a plurality of capacitors connected between a dummy bit line and a complementary dummy bit line in a dummy capacitor region;
• disconnecting the dummy bit line and the complementary dummy bit line from a bit line sense amplifier;
• connecting a bit line and a complementary bit line of a memory cell block to the bit line sense amplifier and sensing memory cell data;
• stopping operation of the bit line sense amplifier and precharging the bit line and the complementary bit line;
• and
• connecting the bit line and the complementary bit line to the dummy bit line and the complementary dummy bit line, respectively.