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US 6,473,348 B2Granted
Data sensing circuit of semiconductor memory
AssigneeSamsung Electronics Co., Ltd.
InventorJae-Yoon Sim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device for performing an effective data sensing operation with a simple constitution. The device comprises first and second blocks each disposed about a sense amplifier and formed of a plurality of bitlines; a circuit for connecting a bitline coupled to memory cell of the first block and a complementary bitline of the second block to the sense amplifier, and charging a bitline coupled to memory cell of the second block and a complementary bitline of the first block up to a predetermined voltage, in response to a signal.
Claims18
A semiconductor memory device, comprising:
- a first and second block each comprising one or more bitlines;
- a sense amplifier;
- and
- a logic means for connecting a bitline connected to a memory cell of the first block to a complementary bitline of the second block in response to a first control signal, and isolating a bitline connected to a memory cell of the second block and a complementary bitline of the first block from the sense amplifier in response to a second control signal,
- wherein a first isolation means connected to the bitline of the first block and a first precharge means connected to the complementary bitline of the first block are synchronously controlled by the first control signal.
2 more elements
A semiconductor memory device, comprising:
- a first and second block each comprising one or more bitlines;
- a sense amplifier;
- a first logic means for connecting a bitline connected to a memory cell of the first block and a complementary bitline of the second block to the sense amplifier in response to a first control signal;
- a second logic means for connecting a bitline connected to a memory cell of the second block and a complementary bitline of the first block to the sense amplifier in response to a second control signal;
- wherein a first isolation means connected to the bitline of the first block and a first precharge means connected to the complementary bitline of the first block are controlled by the first control signal, and
- a third isolation means connected to the complementary bitline of the first block and a third precharge means connected to the bitline of the first block are controlled by the second control signal.
3 more elements
A semiconductor memory device, comprising:
- a first isolation transistor connected between a first bitline and a sense amplifier, responding to a first isolation signal;
- a second isolation transistor connected between a second complementary bitline in the same row with a first complementary bitline and the sense amplifier, responding to the first isolation signal;
- a first precharge transistor connected between the first complementary bitline and reference voltage, responding to the first isolation signal;
- a second precharge transistor connected between a second bitline in the same row with the first bitline and the reference voltage, responding to the first isolation signal;
- a third isolation transistor connected between the first complementary bitline and the sense amplifier, responding to a second isolation signal;
- a fourth isolation transistor connected between the second bitline and the sense amplifier, responding to the second isolation signal;
- a third precharge transistor connected between the first bitline and the reference voltage, responding to the second isolation signal;
- and
- a fourth precharge transistor connected between the second complementary bitline and the reference voltage, responding to the second isolation signal.
6 more elements
A semiconductor memory device, comprising:
- an isolation transistor connecting a bitline to a sense amplifier;
- a precharge transistor connecting the bitline to a reference voltage;
- a conductive line transferring a signal for controlling the isolation and precharge transistors;
- and
- wherein the isolation transistor and the precharge transistor comprise respectively a conductive region formed under each side of the conductive line.
2 more elements
A semiconductor memory device, comprising:
- an isolation transistor connecting a bitline to a sense amplifier;
- a precharge transistor connecting the bitline to a reference voltage;
- a first block region comprising a first and second conductive lines;
- a second block region comprising a third and fourth conductive lines;
- said conductive lines having a finite vertical thickness within said semiconductor, said vertical thickness comprising an upper portion and a lower portion;
- a sense amplifier;
- wherein the first and second conductive lines carry a first and second isolation signals, respectively;
- wherein the third and fourth conductive lines carry a first and second isolation signals, respectively;
- a first conductive region formed under each side of the first conductive line in the first block region for connecting a first bitline to the sense amplifier;
- a second conductive region formed under each side of the second conductive line in the first block region for connecting a first complementary bitline to the sense amplifier;
- a third conductive region formed under each side of the second conductive line in the second block region for connecting a second bitline to the sense amplifier;
- a fourth conductive region formed under each side of the first conductive line in the second block region for connecting a second complementary bitline to the sense amplifier;
- a fifth conductive region formed under each side of the second conductive line in the first block region for connecting the first bitline to the reference voltage;
- a sixth conductive region formed under each side of the first conductive line in the first block region for connecting the first complementary bitline to the reference voltage;
- a seventh conductive region formed under each side of the first conductive line in the second block region for connecting the second bitline to the reference voltage;
- and
- an eighth conductive region formed under each side of the second conductive line in the second block region for connecting the second complimentary bitline to the reference voltage.
14 more elements
Dependencies are inferred from the claim text.