Self burn-in circuit for semiconductor memory

A self burn-in circuit for a semiconductor memory, comprising:

• a burn-in detector circuit for generating a control signal, an address signal, and a test data for a burn-in test operation when said burn-in detector circuit detects a burn-in test condition;
• and
• a memory array for performing the burn-in test operation when said test data is at least one of written into and read from a memory cell which is selected by said address signal in accordance with said control signal, wherein said self burn-in circuit further includes a data comparator for comparing a test data read from said memory array with the test data outputted from said burn-in detector circuit, and wherein said burn-in detector circuit includes:
• a burn-in detector for generating a self burn-in test signal when the burn-in test condition is detected,
• a pulse generator for generating a clock pulse in accordance with the self burn-in test signal applied thereto,
• an address counter for generating the address signal using a clock pulse in accordance with the self burn-in test signal applied thereto,
• a control signal generator for generating RAS, CAS, write enable signal and read enable signal using the clock pulse signal and the address signal in accordance with the self burn-in test signal applied thereto, and
• a data generator for reading the test data from the address signal and for outputting the read data to the data comparator in accordance with the self burn-in test signal from said burn-in detector.