Semiconductor memory device which can be simultaneously tested even when the number of semiconductor memory devices is large and semiconductor wafer on which the semiconductor memory devices are formed

A semiconductor memory device comprising:

• a plurality of memory cells:
• input/output terminals for inputting/outputting data;
• an address terminal receiving an address for making each of said plurality of memory cells active;
• a first control terminal for receiving a first control signal;
• a second control terminal for receiving a second control signal;
• an activating/inactivating circuit for receiving said second control signal as a logical signal when said first control signal has a first logic and outputting an activation signal or an inactivation signal in response to the logic of said second control signal,
• for receiving said second control signal as an analog signal when said first control signal has a second logic and outputting said activation signal or said inactivation signal in response to the value of said analog signal;
• an address decoder decoding an address supplied via said address terminal on the basis of said activation signal and making each of said plurality of memory cells active on the basis of the decoded address;
• and
• an input/output circuit inputting/outputting data to/from the memory cell activated by said address decoder on the basis of said activation signal.

A semiconductor wafer including a plurality of first semiconductor memory devices arranged in the (2n−1)th row (where n is a natural number), a plurality of second semiconductor memory devices arranged in the 2n-th row, and cutting areas, wherein

• each of said plurality of first semiconductor memory devices comprises:
• a plurality of first memory cells;
• a first input/output terminal for inputting/outputting data;
• a first address terminal receiving an address for making each of said plurality of first memory cells active;
• a first control terminal receiving a first control signal for generating an activation signal at the time of writing said data;
• a second control terminal receiving a second control signal for generating an activation signal at the time of reading said data;
• a first activating/inactivating circuit outputting an activation or inactivation signal in response to the logic of said first or second control signal;
• a first address decoder decoding an address received via said address terminal on the basis of said activation signal and activating each of said plurality of memory cells on the basis of the decoded address;
• and
• a first input/output circuit for inputting/outputting data from/to a memory cell activated by said address decoder on the basis of said activation signal, and
• each of said plurality of second semiconductor memory devices comprises:
• a plurality of second memory cells;
• a second input/output terminal for receiving/outputting data;
• a second address terminal receiving an address for making each of said plurality of second memory cells active;
• third control terminal connected to said second control terminal by an interconnection via said cutting area;
• a second activating/inactivating circuit outputting an activation signal or an inactivation signal in response to logic of said second control signal;
• a second address decoder decoding an address supplied via said address terminal on the basis of said activation signal and making each of said plurality of memory cells active on the basis of the decoded address;
• and
• a second input/output circuit inputting/outputting data to/from the memory activated by said address decoder on the basis of said activation signal.

A semiconductor wafer having a plurality of areas each including a plurality of semiconductor memory devices, and a cutting area, wherein

• said cutting area including a selection signal generating circuit for generating a selection signal for activating a plurality of semiconductor memory devices included in each of said plurality of areas in response to logic of a plurality of first control signals, and
• each of said plurality of semiconductor memory devices comprises:
• a plurality of memory cells;
• an input/output terminal for inputting/outputting data;
• an address terminal receiving an address for making each of said plurality of first memory cells active;
• a control terminal receiving said selection signal generated by said selection signal generating circuit;
• an activating/inactivating circuit receiving said selection signal and outputting an activation or inactivation signal in response to the logic of said selection signal;
• an address decoder decoding an address received via said address terminal on the basis of said activation signal and activating each of said plurality of memory cells on the basis of the decoded address;
• and
• an input/output circuit for inputting/outputting data from/to a memory cell activated by said address decoder on the basis of said activation signal.

A semiconductor wafer having a plurality of semiconductor memory devices each including a plurality of memory cells and a cutting area,

• wherein each of said plurality of semiconductor memory devices comprises:
• an output circuit outputting read data from said plurality of memory cells as a digital signal;
• and
• an input circuit writing write data into said plurality of memory cells, and
• said cutting area including an input/output switching circuit for converting a digital signal from said output circuit into an analog signal, outputting said read data as an analog signal, and supplying said write data to said input circuit.