Method for programming EEPROM memory devices with improved reliability, and respective EEPROM memory device

An EEPROM memory device comprising:

• a memory array including a plurality of memory cells, each memory cell comprising a selection transistor and a memory transistor, each said memory transistor having a floating gate region, a drain terminal and a source terminal;
• a plurality of divided source lines;
• a plurality of groups of said memory cells, each group forming a byte;
• at least the memory transistors of the memory cells of a byte having source terminals connected to a same divided source line;
• and
• each said divided source line being connected to a respective switch, each of the respective switches being selectably switchable to couple the respective divided source line with a first or a second voltage potential.

An EEPROM memory device comprising:

• a memory array including a plurality of memory cells, each memory cell comprising a selection transistor and a memory transistor,
• each memory transistor having a floating gate region, a drain terminal and a source terminal,
• a biasing circuit for causing a tunnel current between said floating gate region and said drain terminal of at least one selected cell,
• a turnoff circuit generating a turnoff voltage, said turnoff circuit being connected to said source terminal of said selected cell and activated at the same time as said biasing circuit.

An EEPROM memory device comprising:

• a memory array including a plurality of memory cells, each memory cell comprising a selection transistor and a memory transistor, each said memory transistor having a floating gate region, a drain terminal and a source terminal;
• a plurality of divided source lines;
• plurality of local source lines connected to one of the plurality of divided source lines through a source biasing transistor;
• a plurality of groups of said memory cells, each group forming a byte;
• the memory transistors of the memory cells of a byte having source terminals connected to a same one of the plurality of local source lines;
• and
• each said divided source line being connected to a respective switch.

An EEPROM memory device comprising:

• a memory array including a plurality of memory cells, each memory cell comprising a selection transistor and a memory transistor, each said memory transistor having a floating gate region, a drain terminal and a source terminal;
• a plurality of divided source lines;
• a plurality of groups of said memory cells, each group forming a byte;
• at least the memory transistors of the memory cells of a byte having source terminals connected to a same divided source line;
• a biasing circuit for causing a tunnel current between said floating gate region and said drain terminal of at least one selected cell;
• a turnoff circuit supplying a turnoff voltage;
• each said divided source line being connected to the turnoff circuit through a respective switch;
• and
• a control circuit for simultaneously enabling said turnoff circuit and said biasing circuit.

An EEPROM memory device comprising:

• a memory array including a plurality of memory cells, each memory cell comprising a selection transistor and a memory transistor;
• each memory transistor having a floating gate region, a drain terminal and a source terminal;
• a biasing circuit for causing a tunnel current between said floating gate region and said drain terminal of at least one selected cell;
• a turnoff circuit generating a turnoff voltage, said turnoff circuit being activated at the same time as said biasing circuit;
• and