Redundancy architecture for an interleaved memory
AssigneeSTMicroelectronics S.r.l.
InventorsLuca Giuseppe De Ambroggi, Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Promod Kumar
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Abstract
A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and columns. The redundancy architecture includes a number of packets each including redundancy columns. The packets are divided into two subsets of packets. Each packet is addressable independently from the other by respective address circuits. Each packet also provides redundancy columns exclusively for a respective semi-array.
Claims26
An interleaved memory comprising:
- an array of memory cells divided into a pair of semi-arrays each being singularly addressable and each being organized into rows and columns;
- address circuits for addressing said pair of semi-arrays;
- and
- at least one redundancy packet comprising a plurality of redundancy columns, said at least one redundancy packet being divided into two subsets of redundancy packets and each one being addressable independently from the other by respective address circuits for providing redundancy columns exclusively for one of said pair of semi-arrays.
An interleaved memory comprising:
- an array of memory cells divided into a pair of semi-arrays each being singularly addressable;
- address circuits for addressing said pair of semi-arrays;
- at least one redundancy packet comprising a plurality of redundancy columns, said at least one redundancy packet being divided into two subsets of redundancy packets and each one being addressable independently from the other by respective address circuits for providing redundancy columns exclusively for one of said pair of semi-arrays;
- and
- a plurality of non-volatile memory units containing addresses pointing to symmetrical locations in said pair of semi-arrays where damaged memory cells are to be substituted, one of said plurality of non-volatile memory units storing a most significant bit of a column address pointing to one of said pair of semi-arrays having a damaged memory cell.
An interleaved memory comprising:
- an array of memory cells divided into a pair of semi-arrays each being singularly addressable and each being organized into rows and columns;
- address circuits for addressing said pair of semi-arrays;
- and
- at least one redundancy packet comprising a plurality of redundancy columns, said at least one redundancy packet being divided into two subsets of redundancy packets and each one being addressable independently from the other by respective address circuits for providing redundancy columns exclusively for one of said pair of semi-arrays;
- each address circuit comprising
- a logic gate for each subset of redundancy packets associated with a semi-array for comparing an address directed to one of said pair of semi-arrays with addresses pointing to symmetrical locations of redundant columns in said pair of semi-arrays, and
- a selection switch connected to said logic gate and being configured based upon a most significant bit of a column address pointing to one of said pair of semi-arrays having a damaged memory cell, said selection switch for directing an enable signal to the subset of redundancy packet relative to the one of said pair of semi-arrays having a damaged memory cell.
A method for providing column redundancy for an interleaved memory comprising an array of memory cells divided into a pair of semi-arrays each being singularly addressable, the method comprising:
- dividing at least one redundancy packet comprising a plurality of redundancy columns into two subsets of redundancy packets;
- and
- independently addressing each one of the two subsets of redundancy packets for providing redundancy columns exclusively for one of the pair of semi-arrays.
Dependencies are inferred from the claim text.