Analog voltage supply circuit for a non-volatile memory

An analog voltage supply circuit for a non-volatile memory comprising:

• a write voltage generation circuit which generates a write voltage that is applied to a control gate of a memory cell in said non-volatile memory during a write operation, based on an input analog voltage;
• a verify voltage generation circuit which generates a verify voltage that is applied to said control gate during a verify operation, based on said input analog voltage;
• a source voltage generation circuit having an inverting amplifier which generates a source voltage that is applied to a source of said memory cell during the write operation, wherein said source voltage is changed by varying a gain of said inverting amplifier responsive to a control signal;
• a multi-level sense amplifier circuit which compares a memory cell drain current with a current mirror ratio current of a reference comparison current during the verify operation;
• a counter decoder which outputs a signal equivalent to a number of write pulses applied to said memory cell;
• a comparison circuit which compares an output of said multi-level sense amplifier with the number of write pulses determined by said counter decoder circuit;
• and
• an up-down shift register which shifts a level of said control signals based on a comparison result provided by said comparison circuit.

An analog voltage supply circuit for a non-volatile memory comprising:

• a write voltage generation circuit, having an electric charge distribution condenser and a condenser ratio amplifier, which generates a write voltage that is applied to a control gate of a memory cell in said non-volatile memory during a write operation, based on an input analog voltage, and which changes the write voltage by increasing a voltage of an electrode of the electric charge distribution condenser connected with a negative terminal of the condenser ratio amplifier as well as a voltage of another electrode of the electric charge distribution condenser not connected with the negative terminal of the condenser ratio amplifier, responsive to first control signals;
• a verify voltage generation circuit which generates a verify voltage that is applied to said control gate during a verify operation, based on said input analog voltage;
• a source voltage generation circuit having an inverting amplifier which generates a verify source voltage that is applied to a source of said memory cell during the verify operation, wherein said verify source voltage is changed by varying a gain of said inverting amplifier responsive to second control signals;
• a sense amplifier which compares a memory cell drain current with a reference comparison current during a verify operation;
• a counter decoder circuit which outputs the second control signals which are equivalent to a number of write pulses applied to said memory cell;
• and
• an up-down shift register which shifts a level of said first control signals based on an output of said sense amplifier.

An analog voltage supply circuit for a non-volatile memory comprising:

• a write voltage generation circuit which generates a write voltage that is applied to a control gate of a memory cell in said non-volatile memory during a write operation, based on an input analog voltage;
• a verify voltage generation circuit which generates a verify voltage that is applied to said control gate during a verify operation, based on said input analog voltage;
• a first source voltage generation circuit having a first inverting amplifier which generates a source voltage that is applied to a source of said memory cell during the write operation, wherein said source voltage is changed by changing a gain of said inverting amplifier responsive to first control signals;
• a second source voltage generation circuit having a second inverting amplifier which generates a source voltage that is applied to the source of said memory cell during the verify operation, wherein said verify source voltage is changed by changing a gain of the second inverting amplifier responsive to second control signals;
• a sense amplifier which compares a memory cell drain current with a reference comparison current during the verify operation;
• a counter decoder circuit which outputs the second control signals which are equivalent to a number of write pulses applied to said memory cell;
• and
• an up-down shift register circuit which shifts a level of said first control signals based on an output of said sense amplifier.

An analog voltage supply circuit for a non-volatile memory comprising:

• a write voltage generation circuit, having an electric charge distribution condenser and a condenser ratio amplifier, which generates a write voltage that is applied to a control gate of a memory cell in said non-volatile memory during a write operation, based on an input analog voltage, and which changes the write voltage by increasing a voltage of an electrode of the electric charge distribution condenser connected with a negative terminal of the condenser ratio amplifier as well as a voltage of another electrode of the electric charge distribution condenser not connected with the negative terminal of the condenser ratio amplifier, responsive to first control signals;
• a verify voltage generation circuit which generates a verify voltage that is applied to said control gate during a verify operation, based on said input analog voltage;
• a write memory cell drain voltage generation circuit having a non-inverting amplifier which generates a write memory cell drain voltage during the write operation, said write memory cell drain voltage is changed by varying a gain of the non-inverting amplifier;
• a multi-level sense amplifier which compares a current mirror ratio current of a memory cell drain current with a reference comparison current during the verify operation;
• a counter decoder circuit which outputs a signal equivalent to a number of write pulses applied to said memory cell;
• a comparison circuit which compares an output of said multi-level sense amplifier with the number of write pulses determined by said counter decoder circuit;
• and
• an up-down shift register circuit which shifts a level of said first control signals based on a comparison result provided by said comparison circuit.

An analog voltage supply circuit for a non-volatile memory comprising:

• a write voltage generation circuit, having an electric charge distribution condenser and a condenser ratio amplifier, which generates a write voltage that is applied to a control gate of a memory cell in said non-volatile memory during a write operation, based on an input analog voltage, and which changes the write voltage by increasing a voltage of a positive terminal of the condenser ratio amplifier and the electric charge distribution condenser responsive to control signals;
• a verify voltage generation circuit which generates a verify voltage that is applied to said control gate during verify operation, based on said input analog voltage;
• a write memory cell drain voltage generation circuit having a non-inverting amplifier which generates a write memory cell drain voltage during the write operation, said write memory cell drain voltage is changed by varying a gain of the non-inverting amplifier;
• a multi-level sense amplifier which compares a current mirror ratio current of a memory cell drain current with a reference comparison current during the verify operation;
• a counter decoder circuit which outputs a signal equivalent to a number of write pulses applied to said memory cell;
• a comparison circuit which compares an output of said multi-level sense amplifier with the number of write pulses determined by said counter decoder circuit;
• and
• an up-down shift register circuit which shifts a level of said control signals based on a comparison result provided by said comparison circuit.

An analog voltage supply circuit for a non-volatile memory comprising:

• a write memory cell drain voltage generation circuit, having an electric charge distribution condenser and a condenser ratio amplifier, which generates a write voltage that is applied to a control gate of a memory cell in said non-volatile memory during a write operation, based on an input analog voltage, and which changes the write voltage by increasing a voltage of an electrode of an electric charge distribution condenser connected with a negative terminal of the condenser ratio amplifier as well as a voltage of another electrode of the electric charge distribution condenser not connected with the negative terminal of the condenser ratio amplifier, responsive to control signals;
• a verify voltage generation circuit which generates a verify voltage that is applied to said control gate during a verify operation, based on said input analog voltage;
• a write memory cell drain voltage generation circuit having a non-inverting amplifier which generates a write memory cell drain voltage during the write operation, said write memory cell drain voltage is changed by varying a gain of the non-inverting amplifier;
• a multi-level sense amplifier which compares a memory cell drain current with a current mirror ratio current of a reference comparison current during the verify operation;
• a counter decoder circuit which outputs a signal equivalent to a number of write pulses applied to said memory cell;
• a comparison circuit which compares an output of said multi-level sense amplifier with the number of write pulses determined by said counter decoder circuit;
• and
• an up-down shift register circuit which shifts a level of said control signals based on a comparison result provided by said comparison circuit.

An analog voltage supply circuit for a non-volatile memory comprising:

• a write voltage generation circuit, having an electric charge distribution condenser and a condenser ratio amplifier, which generates a write voltage that is applied to a control gate of a memory cell in said non-volatile memory during a write operation, based on an input analog voltage, and which changes the write voltage by increasing a voltage of a positive terminal of the condenser ratio amplifier and the electric charge distribution condenser responsive to control signals;
• a verify voltage generation circuit which generates a verify voltage that is applied to said control gate during a verify operation, based on said input analog voltage;
• a write memory cell drain voltage generation circuit having a non-inverting amplifier which generates a write memory cell drain voltage during the write operation, said write memory cell drain voltage is changed by varying a gain of the non-inverting amplifier;
• a multi-level sense amplifier which compares a memory cell drain current with a specific current mirror current of a reference comparison current during the verify operation;
• a counter decoder circuit which outputs a signal equivalent to a number of write pulses applied to said memory cell;
• a comparison circuit which compares an output of said multi-level sense amplifier with the number of write pulses determined by said counter decoder circuit;
• and
• an up-down shift register circuit which shifts a level of said control signals based on a comparison result provided by said comparison circuit.