Memory device having memory cells with magnetic tunnel junction and tunnel junction in series
AssigneeHewlett-Packard Company
InventorsLung T. Tran, Manish Sharma, Thomas C. Anthony
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Abstract
A memory device includes dual tunnel junction memory cells having a magnetic tunnel junction in series with a tunnel junction. The magnetic tunnel junction can be changed from a first resistance state to a second resistance state during a write operation. The magnetic tunnel junction can have a differing resistance-voltage characteristic than the tunnel junction, and the differing resistance-voltage characteristics allow the magnetic tunnel junction to be blown without blowing the tunnel junction during a write operation. The change in resistance state of the magnetic tunnel junction changes the resistance of the selected memory cell, which is detectable during a read operation.
Claims11
A memory cell, comprising:
- a first magnetic tunnel junction comprising two magnetic layers and an insulator disposed between the magnetic layers;
- and
- a second tunnel junction comprising an insulator and at least one conductor in series with the first tunnel junction, wherein the first tunnel junction may be changed from a first resistance state to a second resistance state and wherein a resistance of the first tunnel junction decreases more gradually than a resistance of the second tunnel junction when a voltage is developed across the memory cell such that a breakdown voltage of the first tunnel junction is exceeded during a write operation to change the memory cell from the first resistance state to the second resistance state.
A memory array, comprising:
- a substrate;
- an array of memory cells disposed over the substrate;
- a plurality of word lines coupled to the memory cells;
- and
- a plurality of bit lines coupled to the memory, wherein the word lines cross the bit lines at the memory cells, and wherein a memory cell comprises:
- a first magnetic tunnel junction comprising two magnetic layers and an insulator disposed between the magnetic layers;
- and
- a second tunnel junction comprising an insulator and at least one conductor in series with the first tunnel junction, wherein the first tunnel junction may be changed from a first resistance state to a second resistance state and a resistance of the first tunnel junction decreases more gradually than a resistance of the second tunnel junction when a voltage is developed across the memory cell such that a breakdown voltage of the first tunnel junction is exceeded during a write operation to change the memory cell from the first resistance state to the second resistance state.
A method of writing to a memory array comprising an array of memory cells, a plurality word lines coupled to the memory cells, and a plurality of bit lines coupled to the memory cells, each memory cell comprising a magnetic tunnel junction in series with a tunnel junction, the method comprising:
- applying one of a write voltage or a write current to a selected memory cell, wherein a resistance of the magnetic tunnel junction of the selected memory cell is changed from a first state to a second state, wherein the write voltage or write current develops a voltage across the magnetic tunnel junction that is at least equal to a breakdown voltage of the magnetic tunnel junction, and wherein the write voltage or write current develops a voltage across the tunnel junction that is less than a breakdown voltage of the tunnel junction.
Dependencies are inferred from the claim text.