Multi-ported SRAM cell with shared bit and word lines and separate read and write ports

Abstract

A multi-ported SRAM memory cell includes a pair of inverters that holds the data bit. The state terminals of the memory cell connect via a separate read and write data path to the bit lines. The read bit lines connect to a pull-down transistor stack. The first transistor in the stack is gated by the word line, and the second transistor is gated by the state terminal of the memory cell. If the word line is asserted and the second transistor is turned on by the state of the memory cell, the bit line is connected to ground, thus pulling the bit line low. Conversely, if the second transmitter is not turned on, the bit line stays at a high voltage level. In a preferred embodiment, the memory cell is isolated from the pull-down transistor stack by an isolation buffer, such as an inverter, which inverts the voltage on the state terminal of the memory cell. The write data path couples to the memory cell through an access transistor, and also through a second gate that operates to restrict current leakage from the bit lines. In the preferred embodiment, the second gate comprises a current choke that limits current flow to the memory cell during a read operation. Alternatively, the second gate may comprise a transistor that is gated by a write enable signal.

Dependencies are inferred from the claim text.