Storage circuit with layered structure element

A storage circuit comprising a flip-flop, wherein:

• a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel;
• a layered structure of an insulated layer and a semiconductor layer, which is coupled between a gate electrode of a drive gate insulated field effect transistor for either of the first cross couple or the second cross couple and a node outputting a voltage having the same phase as the gate electrode.

A static random access memory device comprising a memory cell that includes a flip-flop, wherein:

• a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel;
• a layered structure of insulated layer and semiconductor layer, which is coupled between a gate electrode of a drive gate insulated field effect transistor for either of the first cross couple or the second cross couple and a node outputting a voltage having the same phase as the gate electrode.