Three-dimensional magnetic memory array with a minimal number of access conductors therein

A magnetic random access memory (MRAM) having a number N of levels of magnetic memory cells, said magnetic memory comprising:

• a plurality of levels of said magnetic memory cells, each level including at least one magnetic memory bit structure having first and second surfaces;
• a bitline conductor connecting to said first surface of said magnetic memory bit structure;
• a wordline conductor connecting to said second surface of said magnetic memory bit structure;
• wherein, N+1 conductors are employed per said number N of levels of said magnetic memory cells.

A semiconductor device comprising a magnetic random access memory (MRAM) having a number N of levels of magnetic memory cells, said magnetic memory comprising:

• a plurality of levels of said magnetic memory cells, each level including at least one magnetic memory bit structure having first and second surfaces;
• a bitline conductor connecting to said first surface of said magnetic memory bit structure;
• a wordline conductor connecting to said second surface of said magnetic memory bit structure;
• wherein, N+1 conductors are employed per said number N of levels of said magnetic memory cells.

A method for forming a magnetic memory having a number N of levels of magnetic memory cells, said method comprising:

• forming a plurality of levels of said magnetic memory cells, each level including at least one magnetic memory core structure having first and second surfaces;
• forming a first access conductor connecting to said first surface;
• forming a second access conductor connecting to said second surface,
• wherein, N+1 access conductors are formed per said number N of levels of said magnetic memory cells.

A method for forming a magnetic random access memory (MRAM) having a number N of levels of magnetic memory cells, said method comprising:

• forming a first bitline conductor;
• forming a first seed layer on said first bitline conductor, said first seed layer comprising a magnetic material;
• forming a first tunnel dielectric layer on said first seed layer;
• forming a first overlying sense layer on said first tunnel dielectric layer;
• patterning said first seed layer, said first tunnel dielectric layer and said first sense layer to form a first magnetic memory bit structure having first and second surfaces, said first surface connecting to said first bitline conductor;
• forming a wordline conductor connecting to said second surface of said first magnetic memory bit structure, said wordline conductor also acting as a second bitline conductor;
• forming a second seed layer on said second bitline conductor, said second seed layer comprising the magnetic material;
• forming a second tunnel dielectric layer on said second seed layer;
• forming a second overlying sense layer on said second tunnel dielectric layer;
• patterning said second seed layer, said second tunnel dielectric layer and said second sense layer to form a second magnetic memory bit structure having first and second surfaces, said first surface connecting to said second bitline conductor;
• repeating the above steps to form said number N of levels of said magnetic memory cells using N+1 conductors.