Semiconductor memory having a pair of bank select drivers driving each bank select line

A semiconductor memory comprising:

• a memory cell array including a number of memory cells arranged in a matrix having a plurality of rows and a plurality of columns;
• a plurality of word lines each connected to a plurality of memory cells of a corresponding row of said plurality of rows in said memory cell array;
• a plurality of bit lines each connected to a plurality of memory cells of a corresponding column of said plurality of columns in said memory cell array;
• a row address decoder fetching an address in response to a row address strobe signal to decode the fetched address and to select one word lines from said plurality of word lines;
• a column address decoder fetching the address in response to a column address strobe signal to decode the fetched address;
• a column selection switch receiving the decoded address from said column address decoder for selecting one bit line from said plurality of bit lines;
• a sense amplifier for precharging the bit line of a memory cell selected by said row address decoder and said column address decoder;
• a precharge circuit for precharging the bit line of a non-selected memory cell;
• and
• a pair of bank select drivers fetching the address in response to said column address strobe signal for raising up a bank select line for turning on a switch between the bit lines and a digit line, said pair of bank select drivers being located at opposite end sides of said bank select line.