Bit line sensing control circuit for a semiconductor memory device and layout of the same

A bit line sensing control circuit for a semiconductor memory device, comprising:

• first and second bit line pairs extending in a first direction, each of the first and second bit line pairs having first and second bit lines;
• a power contact arranged between the first and second bit line pairs;
• a power gate arranged around the power contact;
• a first sense transistor arranged adjacent to an upper-left side of the power gate, having a gate connected to the first bit line of the first bit line pair, a drain connected to the second bit line of the first bit line pair and a source connected to the power contact through the power gate;
• a second sense transistor arranged adjacent to an upper-right side of the power gate, having a gate connected to the second bit line of the first bit line pair, a drain connected to the first bit line of the first bit line pair and a source connected to the power contact through the power gate;
• a third sense transistor arranged adjacent to a lower-left side of the power gate, having a gate connected to the first bit line of the second bit line pair, a drain connected to the second bit line of the second bit line pair and a source connected to the power contact through the power gate;
• a fourth sense transistor arranged adjacent to a lower-right side of the power gate, having a gate connected to the second bit line of the second bit line pair, a drain connected to the first bit line of the second bit line pair and a source connected to the power contact through the power gate;
• a pair of control line contacts arranged in a second direction at an adjacent location outside the first and second bit line pairs to be juxtaposed to the power contact;
• a control line extending in the second direction and connected to the power gate through the pair of control line contacts;
• and
• a power line extending in the second direction adjacent to the control line and connected to an active area surrounded by the power gate through the power contact.

A bit line sensing control circuit for a semiconductor memory device, comprising:

• at least two sense transistors;
• and
• at least one power transistor disposed between said at least two sense transistors, for providing an electrical power to said at least two sense transistors,
• at least two pairs of bit lines,
• wherein the at least one power transistor is disposed between the at least two pairs of bit lines.