System and method for sampling an analog signal level

An electronic signal sampling system comprising:

• an input for receiving an electronic signal;
• a controllable clock source for providing a sampling clock signal;
• a controllable voltage source for providing a reference voltage signal;
• an analog-to-digital converter, electrically coupled to the input, to the controllable clock source, and to the controllable voltage source, and responsive to the sampling clock signal, for comparing the electronic signal relative to the reference voltage signal to provide digital representations of the electronic signal at occurrences of the sampling clock signal;
• an edge sensor for sensing edges of the electronic signal;
• a noise sensor for sensing noise signals included in the electronic signal;
• and
• a controller, coupled to the controllable clock source, the controllable voltage source, the edge sensor, the noise sensor, and the analog-to-digital converter, for adjusting the level of the reference voltage signal and adjusting the phase of the sampling clock signal for finding a voltage level for the reference voltage signal and a phase for the sampling clock signal for comparing the electronic signal to the reference voltage signal at a phase of the sampling clock signal to provide digital representations of the electronic signal at occurrences of the sampling clock signal that are away from an edge of the electronic signal and away from noise signals included in the electronic signal.

A computer readable medium containing computer instructions for a controller to control sampling of an electronic signal as follows:

• (a) sampling an electronic signal by comparing the electronic signal relative to a reference voltage signal to provide digital representations of the electronic signal at occurrences of a sampling clock signal;
• (b) determining a phase for the sampling clock signal where sampling of the electronic signal at the occurrences of the sampling clock signal is away from edges of the electronic signal;
• (c) determining a phase for the sampling clock signal where sampling of the electronic signal at the occurrences of the sampling clock signal is away from noise signals included in the electronic signal;
• and
• (d) selecting a phase for the sampling clock signal that is determined to be both away from the edges of the electronic signal and away from noise signals included in the electronic signal.