Analog to digital conversion circuits, systems and methods with gain scaling switched-capacitor array
AssigneeCirrlus Logic, Inc.
InventorsShyam S Somayajula, Karl Ernesto Thompson
Life of this patent
Estimating the term…
Abstract
A method of gain scaling in a charge redistribution analog to digital converter includes the step of segmenting a bit weighted capacitor array into a first segment having at least one capacitor representing a least significant bit and a second segment having at least one capacitor representing a most significant bit. During a sampling phase, an input signal is sampled onto the at least one capacitor of the second segment while the at least one capacitor of the first segment is coupled to a fixed voltage.
Claims16
A method of gain scaling in switched capacitor circuit comprising the steps of:
- segmenting a bit-weighted capacitor array into a first segment having at least one capacitor representing a least significant bit and a second segment having at least one capacitor representing a most significant bit;
- and
- during a sampling phase, sampling an input signal onto the at least one capacitor of the second segment and coupling the at least one capacitor of the first segment to a differential common mode voltage.
An analog to digital converter comprising:
- a comparator;
- an array of capacitors coupled to an input of said comparator and segmented into a first segment of capacitors representing most significant bits and a second segment of capacitors representing least significant bits;
- and
- switching circuitry operable during a sampling phase to selectively couple said capacitors of said first segment to an analog input of said converter and said capacitors of said second segment to a differential common mode voltage.
An analog to digital converter comprising:
- a data conversion path comprising:
- a comparator having first and second differential inputs;
- a first capacitor array coupled to the first input of the comparator and comprising first and second segments coupled by a bridge capacitor;
- a second capacitor array coupled to the second input of the comparator comprising first and second segments by a bridge capacitor;
- and
- switching circuitry for selectively coupling the first segments of the first and second capacitor arrays to a converter input and the second segments of the first and second capacitors arrays to a differential common mode voltage during a sampling phase.
Dependencies are inferred from the claim text.