Low capacitance, low kickback noise input stage of a multi-level quantizer with dithering and multi-threshold generation for a multi-bit sigma-delta modulator

A multi-bit sigma-delta modulator, comprising:

• a loop filter having an input for coupling to an analog input signal and at least one integrator comprised of an amplifier having an output;
• an N-level quantizer circuit having an analog input terminal coupled to said output of said at least one loop filter amplifier and N−1 digital output terminals, said quantizer further comprising a sampling circuit coupled to said input terminal for sampling said output of said loop filter amplifier for providing a sampled input signal;
• at least one preamplifier stage outputting a first current signal representing said sampled input signal;
• N−1 comparator stages each having an input coupled to first current signal, individual ones of said N−1 comparator stages operating to equally share said first current signal and to compare a shared portion of said first current signal to an associated one of N−1 reference current signals;
• and N−1 dynamic latches individual ones of which latch an output state of one of said N−1 comparators and having an output coupled to one of said N−1 digital output terminals of said quantizer circuit;
• wherein individual ones of said N−1 comparators are constructed using a plurality of common gate configured transistors for suppressing a feedback of noise from said N−1 dynamic latches to others of said comparators and to said input terminal of said quantizer circuit;
• and
• a pseudorandom dither current signal generator having a dither current output signal coupled to said output of said at least one preamplifier stage where said dither current output signal is summed with said first current signal prior to being shared and compared with said associated one of said N−1 reference current signals.

A method for operating an N-level quantizer, comprising steps of:

• sampling an input signal to provide a sampled input voltage signal;
• preamplifying said sampled input signal and outputting a first current signal representing a preamplified sampled input signal;
• adding a dither current signal to said first current signal to generate a dithered first current signal;
• coupling said dithered first current signal to an input terminal of individual ones of N−1 comparator stages;
• dividing said dithered first current signal equally amongst said N−1 comparator stages;
• operating individual ones of said N−1 comparator stages to compare a divided portion of said dithered first current signal to an associated one of N−1 reference current signals;
• and
• latching an output of each of said N−1 comparator stages with a dynamic latch;
• wherein
• individual ones of said N−1 comparators are constructed using a plurality of common gate configured transistors for suppressing a feedback of noise generated by said step of latching to others of said comparators and to an input terminal of said N-level quantizer.

A method for operating an N-level quantizer, comprising steps of:

• sampling a plurality of input signals to provide a plurality of sampled input voltage signals;
• operating a plurality of preamplifiers for preamplifying the sampled input voltage signals and outputting first current signals representing preamplified sampled input voltage signals;
• summing the first current signals by connecting together the outputs of the preamplifiers;
• adding a dither current signal to the sum of the first current signals to generate a dithered sum of the first current signals;
• coupling the dithered sum of the first current signals to an input terminals of individual ones of N−1 comparator stages, where the dithered sum of the first current signals is equally divided between the N−1 comparator stages;
• operating individual ones of the N−1 comparator stages to compare a divided portion of the dithered sum of the first current signals to an associated one of N−1 reference current signals;
• and
• latching an output of each of the N−1 comparator stages with a dynamic latch.