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US 6,473,017 B1Granted
One-bit second order sigma-delta modulator including a polynomial vector quantizer
AssigneeResearch Foundation of the City University of New York
InventorTruong-Thao Nguyen
Life of this patent
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Abstract
A circuit for determining a discrete amplitude of a set of samples xks comprising two integrators that produce integrated signals uk and vk, a converter which supplies an input to the first integrator, timing elements which produce delayed signals uk−1 and vk−1, and a vector quantizer Q(xk, uk−1, vk−1) configured to provide a binary output as a function of samples xk and the integrated signals uk−1 and vk−1.
Claims6
A circuit for determining an amplitude of a set of samples xk comprising:
- a digital to analog converter in a negative feedback loop connected to supply a first integrator input;
- a first integrator acting upon the first integrator input and the set of samples xk, to produce a corresponding set of first integrated signals uk;
- a second integrator acting upon the set of first integrated signals uk to produce a corresponding set of second integrated signals vk;
- timing elements included in a signal, path of the first and second integrated signals uk and vk to provide a delayed first integrated signal uk−i and a delayed second integrated signal vk−1 that are one sample delayed in time relative to the sample xk;
- and
- a vector quantizer Q(xk, uk−1, vk−1) configured to provide a binary output qk in response to the set of samples xk, the delayed first integrated signal uk−1, and the delayed second integrated signal vk−1 inputs
- wherein the vector quantizer Q(xk, uk−1, vk−1) further comprises a quadratic operator acting upon the set of samples xk and the first delayed first integrated signal uk−1 and the delayed second integrated signal vk−1 to produce a summed output yk;
- a set of coefficient boxes acting upon the output zk, the set of samples xk, the delayed first integrated signal uk−1 and the delayed second integrated signal vk−1 to produce a summed output yk, and a comparator receiving the summed output yk as the first comparator input and outputting the binary output qk.
5 more elements
Dependencies are inferred from the claim text.