PWM power amplifier

A PWM power amplifier, comprising:

• a digital signal circuit configured to receive in input a PCM signal with M bits and to convert the PCM signal with oversampling and noise shaping techniques into a PCM digital signal having N bits, where M>N;
• first and second PCM/PWM converters coupled to the digital signal circuit, the converters comprising a counter and a comparator, the counter configured to receive a clock signal and to generate a digital comparison signal, and the comparator configured to receive the digital comparison signal and at least a portion of the PCM digital signal and to generate first and second PWM digital signals as output of the first and second PCM/PWM converters, respectively;
• a clock generator circuit comprising a pulse generator device and an oscillator, the pulse generator device receiving a signal at a frequency equal to a frequency of the PCM signal and to generate output reset pulses, and an oscillator configured to receive the output reset pulses and to generate the clock signal;
• and
• a final stage configured to receive a combination of the first and second PWM digital signals and to provide power amplification thereof in an output.

A PWM power amplifier, comprising:

• a digital signal circuit configured to receive in input a PCM signal with M bits and to convert the PCM signal with oversampling and noise shaping techniques into a PCM digital signal having N bits, where M>N;
• first and second PCM/PWM converters coupled to the digital signal circuit, the converters comprising a counter and a comparator, the counter configured to receive a clock signal and to generate a digital comparison signal, and the comparator configured to receive the digital comparison signal and at least a portion of the PCM digital signal and to generate first and second PWM digital signals as output of the first and second PCM/PWM converters, respectively;
• a clock generator circuit comprising a pulse generator device and an oscillator, the pulse generator device receiving a signal at a frequency equal to a frequency of the PCM signal and to generate output reset pulses, and an oscillator configured to receive the output reset pulses and to generate the clock signal, the clock signal having a clock frequency equal to the product of the first frequency by the power in base two of the number of bits of the PCM signal portion input into one of the first and second PCM/PWM converters, the counter receiving the clock signal and configured to generate the digital comparison output signal in the form of at least one ramp of digital values at an identical or halved frequency compared to the first frequency;
• and
• a final stage configured to receive a combination of the first and second PWM digital signals and to provide power amplification thereof in an output.

A PWM power amplifier, comprising:

• a digital signal circuit configured to receive in input a PCM signal with M bits and to convert the PCM signal with oversampling and noise shaping techniques into a PCM digital signal having N bits, where M>N;
• first and second PCM/PWM converters coupled to the digital signal circuit, the converters comprising a counter and a comparator, the counter configured to receive a clock signal and to generate a digital comparison signal, and the comparator configured to receive the digital comparison signal and at least a portion of the PCM digital signal and to generate first and second PWM digital signals as output of the first and second PCM/PWM converters, respectively;
• a clock generator circuit comprising a pulse generator device and an oscillator, the pulse generator device receiving a signal at a first frequency equal to a frequency of the PCM signal and to generate output reset pulses, and an oscillator configured to receive the output reset pulses and to generate the clock signal, the clock signal having a frequency equal to the product of the first frequency by the power in base two of the number of bits of the PCM signal received by one of the first and second PCM/PWM converters, each of the first and second PCM/PWM converters comprising a double ramp type converter receiving the clock signal, and each counter being of the up/down type and having in input a ramp conversion signal and configured to generate in output the digital comparison signal comprising the number of bits of the portion of the PCM signal received by the respective counter, and further in the form of a succession of up and down ramps at a halved frequency of the first frequency;
• and
• a first final stage configured to receive a combination of the first and second PWM digital signals and to provide power amplification thereof in an output, and a second final stage that is a duplicate of the first final stage and functioning in counter phase thereof and having an inversion signal input that receives an inversion of a combination of the PWM digital signals that is generated by a second and third pair of PCM/PWM double ramp converters that are duplicates of the first and second PCM/PWM converters and having the ramp inversion signal inverted and to generate a power amplification thereof.