Voltage controlled oscillator with delay circuits

A voltage-controlled oscillator comprising:

• a plurality of basic cells;
• and
• a center frequency adjustment circuit that outputs a control signal for setting a delay time for each of said plurality of basic cells;
• each of said basic cells comprising:
• first and second cell input terminals;
• first and second cell output terminals from which signals that have been received from said first and second cell input terminals are outputted in non-inverted form;
• a first delay circuit for delaying signals received from said first and second cell input terminals by a delay time that is set based on the control signal outputted from said center frequency adjustment circuit;
• a second delay circuit for delaying output signals of said first delay circuit by a delay time that is set independently of said first delay circuit based on the control signal outputted from said center frequency adjustment circuit;
• and
• an adder circuit that adds said output signals of said first delay circuit and output signals from said second delay circuit at a proportion that is based on an additional proportion coefficient that is controlled from outside and outputs a result of addition;
• wherein, in each of said basic cells, said result of addition is applied to said first and second cell output terminals;
• and
• the basic cells are connected in a series such that said first and second cell output terminals of a preceding-stage basic cell are connected to said first and second cell input terminals, respectively, of the next-stage basic cell, and said first and second cell output terminals of the last-stage basic cell are connected to the second and first cell input terminals, respectively, of the first-stage basic cell such that logic is reversed;
• wherein each of said delay circuits comprises:
• first and second input terminals;
• first and second output terminals from which signals that have been applied to said first and second input terminals are each outputted in non-inverted form with a prescribed delay time that is based on the control signal outputted from said center frequency adjustment circuit;
• a first MOS (Metel-Oxide-Semiconductor) transistor having a gate connected to said first input terminal, and a drain connected to both a first power-supply voltage by way of a first resistor and to said second output terminal;
• a second MOS transistor having a gate connected to said second input terminal, and a drain connected to both the first power-supply voltage by way of a second resistor and to said first output terminal;
• a third MOS transistor having a gate connected to said drain of said first MOS transistor, and a drain connected to said drain of said second MOS transistor;
• a fourth MOS transistor having a gate connected to said drain of said second MOS transistor, and a drain connected to said drain of said first MOS transistor;
• a fifth MOS transistor having a source connected to a second power-supply voltage having a different potential from said first power-supply voltage, a drain connected in common to said sources of said first and second MOS transistors, and a gate connected to said center frequency adjustment circuit;
• and
• a sixth MOS transistor having a source connected to said second power-supply voltage, a drain connected in common to said sources of said third and fourth MOS transistors, and a gate connected to said center frequency adjustment circuit.

A voltage-controlled oscillator comprising;

• a plurality of basic cells;
• and
• a center frequency adjustment circuit that outputs a control signal for setting a delay time for each of said plurality of basic cells;
• each of said basic cells comprising:
• first and second cell input terminals;
• first and second cell output terminals from which signals that have been received from said first and second cell input terminals are outputted in non-inverted form;
• a first delay circuit for delaying signals received from said first and second cell input terminals by a delay time that is set based on the control signal outputted from said center frequency adjustment circuit;
• a second delay circuit for delaying output signals of said first delay circuit by a delay time that is set independently of said first delay circuit based on the control signal outputted from said center frequency adjustment circuit;
• and
• an adder circuit that adds said output signals of said first delay circuit and output signals from said second delay circuit at a proportion that is based on an additional proportion coefficient that is controlled from outside and outputs a result of addition;
• wherein, in each of said basic cells, said result of addition is applied to said first and second cell output terminals;
• and
• the basic cells are connected in a series such that said first and second cell output terminals of a preceding-stage basic cell are connected to said first and second cell input terminals, respectively, of the next-stage basic cell, and said first and second cell output terminals of the last-stage basic cell are connected to the second and first cell input terminals, respectively, of the first-stage basic cell such that logic is reversed;
• wherein each of said delay circuit comprises:
• first and second input terminals;
• first and second output terminals from which signals that have been received at said first and second input terminals are each outputted in non-inverted form with a prescribed delay time based on the control signals outputted from said center frequency adjustment circuit;
• first and second PMOS (P-channel Metal-Oxide-Semiconductor) transistors having drains each connected to a first power-supply voltage, and gates connected in common to an auxiliary power-supply voltage;
• a first NMOS (N-channel Metel-Oxide-Semiconductor) transistor having a gate connected to said first input terminal, and a drain connected to both said source of said first PMOS transistor and to said second output terminal;
• a second NMOS transistor having a gate connected to said second input terminal, and a drain connected to both said source of said second PMOS transistor and to said first output terminal;
• a third NMOS transistor having a gate connected to said drain of said first NMOS transistor, and a drain connected to said drain of said second NMOS transistor;
• a fourth NMOS transistor having a gate connected to said drain of said second NMOS transistor, and a drain connected to said drain of said first NMOS transistor;
• a fifth NMOS transistor having a source connected to a second power-supply voltage, a drain connected in common to said sources of said first and second NMOS transistors, and a NMOS transistors, and a gate connected to said center frequency adjustment circuit;
• and
• a sixth NMOS transistor having a source connected to said second power-supply voltage, a drain connected in common to said sources of said third and fourth NMOS transistors, and a gate connected to said center frequency adjustment circuit.