Parasitically compensated resistor for integrated circuits
AssigneeEM (US) Design, Inc.
InventorsJames Harold Lauffenburger, John William Arachtingi, Kevin Scott Buescher, Gil Afriat
Life of this patent
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Abstract
A parasitically compensated resistor (50) for integrated circuits includes a substrate (52). A polysilicon resistor (54) is formed in the substrate (52). The polysilicon resistor (54) has a first end connected to a first lead (56) and a second end connected to a second lead (58). A conductive layer (62) is capacitively connected to the polysilicon resistor (54).
Claims13
A transimpedance amplifier integrated circuit having a parasitically compensated resistor, comprising:
- a current source;
- an operational amplifier having an inverting input connected to the current source and an non-inverting input connected to a ground;
- a semiconductor resistor connected between an output of the operational amplifier and the inverting input;
- and
- a conductive layer capacitively coupled to the semiconductor resistor and electrically connected to the output of the operational amplifier but not electrically connected to the inverting input.
A method of forming a parasitically compensated resistor for a transimpedance amplifier integrated circuit, comprising:
- a) determining a desired feedback resistance;
- b) determining a parasitic capacitance associated with the desired feedback resistance;
- c) calculating a pole location for the desired feedback resistance and the parasitic capacitance;
- d) determining a compensation capacitance necessary to create a zero location to negate the pole location;
- and
- e) creating a feedback resistor having the desired feedback resistance and a compensation capacitor with the compensation capacitance.
The method of claim wherein step (e2) further includes the step of:
- i) creating an n-well in the substrate adjacent to the polysilicon layer.
Dependencies are inferred from the claim text.