Low power supply CMOS differential amplifier topology
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A structure and method for improving differential amplifier operation is provided. High performance, wide bandwidth or very fast CMOS amplifiers are possible using the new circuit topology of the present invention. The differential amplifier of the present invention employs a novel common mode feedback circuit to back bias the body regions of the amplifying transistors in the differential amplifier. The novel configuration is achieved entirely using CMOS fabrication techniques and delivers high performance in both amplifier gain (G) and frequency response (fT) characteristics using a 1 micron (1 μ) CMOS technology.
Claims28
A method for operating a signal processing circuit, comprising:
- biasing a gate of a first MOSFET in a first amplifying circuit;
- biasing a gate of a second MOSFET in the first amplifying circuit;
- applying a first input signal to the gate of the first MOSFET applying a second input signal to the gate of the second MOSFET;
- and
- coupling a bias from an output of a common mode feedback circuit to a body region in each of the first and second MOSFETs, respectively.
A method for operating an analog circuit, comprising:
- biasing a gate of a first MOSFET in a first amplifying circuit;
- biasing a gate of a second MOSFET in the first amplifying circuit;
- applying a first input signal to the gate of the first MOSFET applying a second input signal to the gate of the second MOSFET;
- coupling a first load device to a drain region of the first MOSFET and a second load device to a drain region of the second MOSFET;
- and
- coupling a bias from an output of a common mode feedback circuit to a body region in each of the first and second MOSFETs, respectively.
A method for operating an analog circuit, comprising:
- biasing a gate of a first MOSFET in a first amplifying circuit;
- biasing a gate of a second MOSFET in the first amplifying circuit;
- applying an input signal to the gate of the first MOSFET;
- coupling a first load device to a drain region of the first MOSFET and a second load device to a drain region of the second MOSFET;
- and
- coupling a bias from an output of a common mode feedback circuit to a body region in each of the first and second MOSFETs, respectively.
A method for operating a single integrated circuit, comprising:
- processing a signal through a digital logic circuit;
- processing a signal through an analog circuit, including:
- biasing a gate of a first MOSFET in a first amplifying circuit;
- biasing a gate of a second MOSFET in the first amplifying circuit;
- applying a first input signal to the gate of the first MOSFET
- applying a second input signal to the gate of the second MOSFET;
- and
- coupling a bias from an output of a common mode feedback circuit to a body region in each of the first and second MOSFETs, respectively.
A method for operating a single integrated circuit, comprising:
- processing a signal through a digital logic circuit;
- processing a signal through an analog circuit, including:
- biasing a gate of a first MOSFET in a first amplifying circuit;
- biasing a gate of a second MOSFET in the first amplifying circuit;
- applying an input signal to the gate of the first MOSFET;
- and
- coupling a bias from an output of a common mode feedback circuit to a body region in each of the first and second MOSFETs, respectively.
A method for operating an electronic system, comprising:
- accessing a memory circuit;
- processing a signal from the memory circuit, including:
- biasing a gate of a first MOSFET in a first amplifying circuit;
- biasing a gate of a second MOSFET in the first amplifying circuit;
- applying a first input signal to the gate of the first MOSFET
- applying a second input signal to the gate of the second MOSFET;
- and
- coupling a bias from an output of a common mode feedback circuit to a body region in each of the first and second MOSFETs, respectively.
A method for operating an electronic system, comprising:
- accessing a memory circuit;
- processing a signal from the memory circuit, including:
- biasing a gate of a first MOSFET in a first amplifying circuit;
- biasing a gate of a second MOSFET in the first amplifying circuit;
- applying an input signal to the gate of the first MOSFET;
- and
- coupling a bias from an output of a common mode feedback circuit to a body region in each of the first and second MOSFETs, respectively.
Dependencies are inferred from the claim text.