Switching amplifier incorporating return-to-zero quaternary power switch

A quaternary switching amplifier comprising:

• a switching control circuit including a multi-level nth sigma-delta modulator circuit to generate a quaternary input signal, the multi-level nth sigma-delta modulator circuit having
• an input summer circuit,
• a first integrator circuit coupled to the input summer circuit,
• n−1 integrator circuits where the nth integrator circuit is coupled to an output of the (n−1)th integrator circuit, n>1,
• a second summer circuit coupled to the output of the first integrator circuit and an output of the n−1 integrator circuits to generate a second summer circuit output,
• a multi-level quantizer coupled to receive the output of the second summer circuit and generating an output signal of the multi level quantizer comprising a multi level sequence of states ( . . . +3, +2, +1, 0, −1, −2, −3, . . . ), and
• a control circuit coupled to receive the output of the multi-level quantizer and generate the quaternary input signal, wherein the first input summer circuit is coupled to receive a switching amplifier input signal and the multi-level quantizer output signal to convert the switching amplifier input signal to a ternary state output signal;
• and
• an H-bridge circuit, the H-bridge circuit is coupled to receive the quaternary input signal, the H-bridge further comprising four input control signal ports coupled to receive the quaternary input signal to control an amplifier output of the H-bridge circuit to swing between a positive state (+1) and a negative state (−1) and to provide error cancellation in the amplifier output of the H-bridge circuit.

A quaternary switching amplifier method comprising:

• coupling a quaternary switching amplifier input signal to a switch control circuit that generates a quaternary output signal;
• and
• coupling the quaternary output signal to an H-bridge circuit to provide error cancellation in an output of the H-bridge circuit, the coupling of the quaternary output signal to the H-bridge further comprising
• switching two pairs of transistors to achieve one of four amplifier output states comprising a (+1) state, a (−1) state, a (0H) state, and a (0L) state, wherein between the (+1) state and the (−1) state, switching amplifier is switched either to the (0H) state or the (0L) state depending on the preceding switched output state, and
• wherein the step of switching to the (+1) state comprises synchronizing switching close a first transistor (AH) and a fourth transistor (BL), while synchronizing switching open a second transistor (AL) and a third transistor (BH),
• wherein the step of switching to the (0H) state comprises synchronizing switching dose AH and BH, while synchronizing switching open AL and BL,
• wherein the step of switching to the (−1) state comprises synchronizing switching open AH and BL, while synchronizing switching close AL and BL, and
• wherein the step of switching to the (0L) state comprises synchronizing switching open AH and BH, while synchronizing switching close AL and BL.

A quaternary switching amplifier comprising:

• two pairs of switches, a first pair of switches comprising a first transistor (AH) and a second transistor (AL), and a second pair of switches comprising a third transistor (BH) and a fourth transistor (BL);
• a load coupled to the two pairs of switches via a positive node (V+) and a negative node (V−);
• an output of the switch amplifier comprising a voltage difference across the load, between the node (V+) and the node (V−);
• and
• wherein each transistor comprises a first terminal, a second terminal, and a third input switch control terminal, with a first terminal of transistors AH and BH coupled to a positive power supply (VP), and a second terminal of transistor AH coupled to the load via the positive node V+ and the second terminal of BH coupled to the load via negative node V−;
• wherein a first terminal of AL and BL coupled to a negative power supply (VM), and the second terminal of transistor AL is coupled to the load via node V+ and a second terminal of BL is coupled to the load via node V−;
• and
• wherein the third input switch control terminal of each transistor is coupled to a clock signal to receive an quaternary input clock signal alternating between a 0H state and a 0L state between each positive +1 or negative −1 amplifier output state.